Sojus07/hackrf
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12 Commits

Author SHA1 Message Date
TitanMKD
fa47f8af8c Fix for IQ problem for ADC: 
RX samples are ordered I0,Q1,I1,Q2,I2,... where they should be I0,Q0,I1,Q1,I2,Q2,...
This fix also alias/ghost problems to be confirmed on other boards/more tests...
Drawback now IQ is QI, will be fixed/swapped in LPC4330 SGPIO code.
 2013-04-04 00:55:51 +02:00
Jared Boone
672e37d040 Added .jed (programmer file) so we can build SVF or XSVF from the bitstream as needed. 
Updated SVF due to "changed" .jed.
Added XSVF for future in-system programming of CPLD.
 2013-02-14 12:13:33 -08:00
Jared Boone
4878be8213 New .svf to reflect slew rate and IO standard changes in prior commits. 
Changed name of .svf file to "default.svf" to match what ISE iMPACT wants to write out from "One Step SVF" (a.k.a. "Expresssvf").
 2012-07-24 13:27:19 -07:00
Jared Boone
5ab31b84e0 Remove FAST attribute from all CPLD I/O, since it changes slew rate by less than 1ns -- not enough to be important at 20MHz or so. Will re-examine later, if we try to push bus speed higher on the final board rev. 2012-07-24 12:48:08 -07:00
Jared Boone
18587e3732 Change all IO on CPLD to LVCMOS33 until we make the move to 1V8 supplies on the MAX5864 and Si5351C. 2012-07-24 12:45:46 -07:00
Jared Boone
892f4c1eea Added link to Dangerous Prototypes information on how to switch buffers in Bus Blaster v2. 2012-07-19 16:50:58 -07:00
Jared Boone
6121294550 Moved BSDL requirement to "program" requirements. 2012-07-19 16:48:09 -07:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
d68036f79d Eliminate ill-conceived HOST_CLK from CPLD. 
Rearrange clocks to not use AC-coupled CLK1 from Si5351C.
Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2.
Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.
 2012-06-14 19:08:20 -07:00
Jared Boone
9c50b7de26 Updated SVF from committed project files. 2012-06-09 22:34:32 -07:00
Jared Boone
89314d40d6 Added Bus Blaster programming script. Added README explaining project contents and programming process. 2012-06-09 22:34:01 -07:00
Jared Boone
07b6f81a6c Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD. 2012-06-09 22:02:45 -07:00