Added link to Dangerous Prototypes information on how to switch buffers in Bus Blaster v2.
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@ -11,7 +11,7 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:
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To program the SVF file into the CPLD:
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* Dangerous Prototypes Bus Blaster v2:
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* Configured with JTAGKey buffers.
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* Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic).
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* Connected to CPLD JTAG signals on Jellybean.
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* urJTAG built with libftdi support.
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