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595 Commits

Author SHA1 Message Date
Jared Boone
0ddb4cb7f2 Configure LPC43xx for GP_CLKIN input. 2013-12-31 20:07:11 -08:00
Jared Boone
1bec883f80 Add baseband sampling frequencies useful for 48kHz audio output. 2013-12-31 20:05:26 -08:00
Michael Ossmann
06f98a3968 reverted a2e436e from incorrect merge 2013-12-24 23:14:17 -07:00
Michael Ossmann
a2e436e3a8 tester changes 2013-12-20 14:44:21 -07:00
Michael Ossmann
6b482b94da set crystal load capacitance to 8 pF 2013-12-12 15:47:00 -07:00
Michael Ossmann
355597d9e6 swapped CPLD JTAG pins for HackRF One 20131127 2013-12-09 19:06:24 -07:00
Jared Boone
9f2260237b Add GPDMA LLI functions to create a loop or one-shot chain of LLIs. 2013-12-08 18:18:22 -08:00
Jared Boone
5b59f9cb0a Change GPDMA channel clli member to uint32_t, casting to/from gpdma_lli_t and dealing with the multiple fields was driving me crazy. 2013-12-08 18:16:58 -08:00
Jared Boone
6185b67008 Add GPDMA LLI function to enable interrupt after LLI operation is complete. 2013-12-08 17:49:50 -08:00
Jared Boone
ca070acad0 Expose SGPIO DMA LLI configuration function. 
Remove LLI declarations internal to SGPIO DMA module.
Require a start LLI for SGPIO DMA start functions.
 2013-12-08 13:14:26 -08:00
Jared Boone
ea2ca52301 Rename SGPIO DMA internal function to match style of public functions. 2013-12-08 13:07:32 -08:00
Jared Boone
ac0d50a131 Remove irrelevant assumption that LLI argument is a pointer to an array. 2013-12-08 13:06:14 -08:00
Jared Boone
d2fd5e74c5 Change SGPIO DMA configuration API from dividing up a buffer's length into M parts to creating a chain of M transfers of size N. 2013-12-08 13:05:30 -08:00
Jared Boone
6196fa2810 Move LLI_COUNT constant out of SGPIO DMA utility functions. 2013-12-08 12:50:20 -08:00
Jared Boone
2fab6c40cd Extract SGPIO multi_slice configuration argument into an init-time function, so it doesn't need to be passed each time the SGPIO interface direction is changed. 2013-12-08 12:21:41 -08:00
Jared Boone
50ec268794 Bracket SGPIO GPDMA slice configuration with multislice==false test. It only makes sense in single slice mode (until I have a clever idea for doing GPDMA with multiple slices). 2013-12-08 12:14:00 -08:00
Jared Boone
809df425c1 Add SGPIO configuration to support GPDMA interrupts. 2013-12-08 11:54:50 -08:00
Jared Boone
45c0a6c31a Extract/isolate path details in Makefile_inc.mk. 2013-12-08 11:33:47 -08:00
Jared Boone
f51ee2dc61 Modified ldscripts to more accurately represent LPC4330 hardware. 
Moved M0 RAM from local to AHB.
Created separate region for sleep RAM.
 2013-12-07 15:29:50 -08:00
Jared Boone
34b01d89af Add SGPIO DMA configuration code. 2013-12-07 15:29:14 -08:00
Jared Boone
3e7ff530d7 Add GPDMA API. Should go in libopencm3 when it's more fleshed-out. 2013-12-07 15:28:59 -08:00
Michael Ossmann
040aafc399 blinky update for HackRF One 2013-11-27 02:33:45 -07:00
Michael Ossmann
99803c26cb another clock strength adjustment 2013-11-22 17:50:10 -07:00
Michael Ossmann
ebaccf46f4 adjusted clock generator output drive strength 2013-11-22 17:24:53 -07:00
Jared Boone
5468a01a9b Forgot to include rf_path.h now that its pin setup is called from hackrf_core. 2013-11-21 10:23:53 -08:00
Jared Boone
b285b91e4c Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/hackrf_core.h
	firmware/common/rffc5071.c
 2013-11-20 18:43:40 -08:00
Jared Boone
9db166427f Remove I2S pin definitions, since they're too specific for generic/shared HackRF code. 2013-11-20 15:46:53 -08:00
Jared Boone
f453e4c377 Bump libopencm3. 2013-11-20 15:44:15 -08:00
Jared Boone
986e4dec93 Massive rework of Makefile_inc.mk, to support building of heterogeneous (M4+M0) binaries, and easy switching between RAM and SPIFI-bootable builds. Constructive criticism welcome -- I'm sure there's better ways to do this. 2013-11-20 15:28:28 -08:00
Jared Boone
02ba23bf68 Fix broken sgpio-rx project, broken due to massive changes to how RF path and tuning is done. 2013-11-20 15:24:50 -08:00
Jared Boone
893c20e41f Fix naming problem with SGPIO test project. This is due to my use of VPATH in Makefile_inc.mk, which I'm starting to regret a little bit... 2013-11-20 15:24:14 -08:00
Jared Boone
552dbe4a6d Add sgpio.c to C files, now required for pin initialization. 2013-11-20 15:23:26 -08:00
Jared Boone
6a03f157ff With Makefile RAM/SPIFI option, remove/rework redundant "rom_to_ram" projects. 2013-11-20 15:21:40 -08:00
Jared Boone
c365d0a37e Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region. 2013-11-20 15:14:13 -08:00
Jared Boone
31a55d0e9b Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now... 2013-11-20 15:13:18 -08:00
Jared Boone
e29ec6b084 Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files. 2013-11-20 15:11:54 -08:00
Jared Boone
91a7ca4983 Fix return value on SGPIO decimation function. 2013-11-20 15:08:59 -08:00
Jared Boone
e3f9e204c1 Relocate SGPIO pin configuration -- it only needs to be done once. 2013-11-20 13:22:19 -08:00
Jared Boone
39276f162c Add M0 linker script. 2013-11-19 19:52:50 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller. 
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
 2013-11-19 19:52:06 -08:00
Jared Boone
24a8e2bdb5 Remove CPLD SVF file, as it's not used by anybody (as far as I know). 2013-11-19 19:45:36 -08:00
Michael Ossmann
5b14636c2c initial firmware support for HackRF One 2013-11-19 10:01:26 -07:00
Jared Boone
967e699815 Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values. 2013-11-17 22:23:08 -08:00
Jared Boone
d006ec769c Updated CPLD bitstream with two's complement I/O and sample ordering fix. 2013-11-16 13:41:54 -08:00
Jared Boone
89eafaa79a Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this. 2013-11-16 13:32:41 -08:00
Jared Boone
7ef9c1e932 Slow down edges of data lines coming from CPLD. 2013-11-16 13:31:19 -08:00
Jared Boone
147f47a3f5 Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed. 
Do conversion from unsigned to two's-compliment inside FPGA.
 2013-11-16 13:29:00 -08:00
Jared Boone
9856ea3d14 Changes due to CGU header API changes. 2013-11-15 11:41:20 -08:00
Jared Boone
4917c5019a Additional CGU register decoding in dump_cgu.py. 2013-11-02 22:51:35 -07:00
Jared Boone
06da7fd83a Reduce drive strength from clock generator (Si5351C) to first mixer (RFFC5072). This reduces every-50MHz spurs in RX by 10 to 15dB. 2013-09-22 11:54:37 -07:00