Sojus07/hackrf
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,465 Commits 1 Branch 0 Tags
Commit Graph

324 Commits

Author SHA1 Message Date
Jared Boone
936e356040 ldscript memory region clean-up for LPC4330 targets. 2014-01-11 15:49:46 -08:00
Jared Boone
095f55abce Make a bit of room in the M0 AHB RAM region for fixed-location shared (M4, M0 cores) data structures. 2014-01-11 15:21:20 -08:00
Jared Boone
80047c9a0c Makefile: Add separate OBJ_M4_S and OBJ_M0_S variables for .S files. (Unused, but worked earlier and may be useful later.) 2014-01-11 15:20:10 -08:00
Jared Boone
fb5dc6d5e0 Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/si5351c.c

Preferred Si5351C configuration that drives 40MHz into the LPC43xx GP_CLKIN.
Added HACKRF_ONE qualifier for CPLD TMS/TDI swap.
 2014-01-07 16:48:52 -08:00
Jared Boone
75e1dcd9cf Don't update MAX2837 freq_cache unless set_freq() is successful. 2014-01-04 10:15:01 -08:00
Jared Boone
dbba407069 Change M0 linking to use newlib-nano. snprintf() is a pig when the floating point junk gets pulled in on an M0... 2014-01-02 15:11:15 -08:00
Jared Boone
63292419c8 Moved M0 memory region to larger first AHB region (32K), moved USB bulk buffers to smaller AHB RAM area. 2014-01-02 15:10:09 -08:00
Jared Boone
c6b1ec2979 Adjust SGPIO GPDMA trigger slice data to a single clock width pulse. Previously, it was 3 clocks long with a 4 clock period, which *seemed* to address GPDMA data drop-outs at maximum baseband speed (20Msps complex). 2013-12-31 20:27:14 -08:00
Jared Boone
fc5ec03353 Adjust tuning API to use a single 64-bit integer for frequency in Hz, since the Cortex-M4F has good support for uint64_t. 2013-12-31 20:12:47 -08:00
Jared Boone
7f35ceaff2 Set Si5351C CLK7 output to drive LPC GP_CLKIN at 40MHz, so that activity (e.g. audio) on the LPC can be synchronized with the baseband sample rate. 2013-12-31 20:09:44 -08:00
Jared Boone
0ddb4cb7f2 Configure LPC43xx for GP_CLKIN input. 2013-12-31 20:07:11 -08:00
Jared Boone
1bec883f80 Add baseband sampling frequencies useful for 48kHz audio output. 2013-12-31 20:05:26 -08:00
Michael Ossmann
6b482b94da set crystal load capacitance to 8 pF 2013-12-12 15:47:00 -07:00
Michael Ossmann
355597d9e6 swapped CPLD JTAG pins for HackRF One 20131127 2013-12-09 19:06:24 -07:00
Jared Boone
9f2260237b Add GPDMA LLI functions to create a loop or one-shot chain of LLIs. 2013-12-08 18:18:22 -08:00
Jared Boone
5b59f9cb0a Change GPDMA channel clli member to uint32_t, casting to/from gpdma_lli_t and dealing with the multiple fields was driving me crazy. 2013-12-08 18:16:58 -08:00
Jared Boone
6185b67008 Add GPDMA LLI function to enable interrupt after LLI operation is complete. 2013-12-08 17:49:50 -08:00
Jared Boone
ca070acad0 Expose SGPIO DMA LLI configuration function. 
Remove LLI declarations internal to SGPIO DMA module.
Require a start LLI for SGPIO DMA start functions.
 2013-12-08 13:14:26 -08:00
Jared Boone
ea2ca52301 Rename SGPIO DMA internal function to match style of public functions. 2013-12-08 13:07:32 -08:00
Jared Boone
ac0d50a131 Remove irrelevant assumption that LLI argument is a pointer to an array. 2013-12-08 13:06:14 -08:00
Jared Boone
d2fd5e74c5 Change SGPIO DMA configuration API from dividing up a buffer's length into M parts to creating a chain of M transfers of size N. 2013-12-08 13:05:30 -08:00
Jared Boone
6196fa2810 Move LLI_COUNT constant out of SGPIO DMA utility functions. 2013-12-08 12:50:20 -08:00
Jared Boone
2fab6c40cd Extract SGPIO multi_slice configuration argument into an init-time function, so it doesn't need to be passed each time the SGPIO interface direction is changed. 2013-12-08 12:21:41 -08:00
Jared Boone
50ec268794 Bracket SGPIO GPDMA slice configuration with multislice==false test. It only makes sense in single slice mode (until I have a clever idea for doing GPDMA with multiple slices). 2013-12-08 12:14:00 -08:00
Jared Boone
809df425c1 Add SGPIO configuration to support GPDMA interrupts. 2013-12-08 11:54:50 -08:00
Jared Boone
45c0a6c31a Extract/isolate path details in Makefile_inc.mk. 2013-12-08 11:33:47 -08:00
Jared Boone
f51ee2dc61 Modified ldscripts to more accurately represent LPC4330 hardware. 
Moved M0 RAM from local to AHB.
Created separate region for sleep RAM.
 2013-12-07 15:29:50 -08:00
Jared Boone
34b01d89af Add SGPIO DMA configuration code. 2013-12-07 15:29:14 -08:00
Jared Boone
3e7ff530d7 Add GPDMA API. Should go in libopencm3 when it's more fleshed-out. 2013-12-07 15:28:59 -08:00
Michael Ossmann
99803c26cb another clock strength adjustment 2013-11-22 17:50:10 -07:00
Michael Ossmann
ebaccf46f4 adjusted clock generator output drive strength 2013-11-22 17:24:53 -07:00
Jared Boone
5468a01a9b Forgot to include rf_path.h now that its pin setup is called from hackrf_core. 2013-11-21 10:23:53 -08:00
Jared Boone
b285b91e4c Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/hackrf_core.h
	firmware/common/rffc5071.c
 2013-11-20 18:43:40 -08:00
Jared Boone
9db166427f Remove I2S pin definitions, since they're too specific for generic/shared HackRF code. 2013-11-20 15:46:53 -08:00
Jared Boone
986e4dec93 Massive rework of Makefile_inc.mk, to support building of heterogeneous (M4+M0) binaries, and easy switching between RAM and SPIFI-bootable builds. Constructive criticism welcome -- I'm sure there's better ways to do this. 2013-11-20 15:28:28 -08:00
Jared Boone
c365d0a37e Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region. 2013-11-20 15:14:13 -08:00
Jared Boone
31a55d0e9b Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now... 2013-11-20 15:13:18 -08:00
Jared Boone
e29ec6b084 Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files. 2013-11-20 15:11:54 -08:00
Jared Boone
91a7ca4983 Fix return value on SGPIO decimation function. 2013-11-20 15:08:59 -08:00
Jared Boone
e3f9e204c1 Relocate SGPIO pin configuration -- it only needs to be done once. 2013-11-20 13:22:19 -08:00
Jared Boone
39276f162c Add M0 linker script. 2013-11-19 19:52:50 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller. 
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
 2013-11-19 19:52:06 -08:00
Michael Ossmann
5b14636c2c initial firmware support for HackRF One 2013-11-19 10:01:26 -07:00
Jared Boone
967e699815 Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values. 2013-11-17 22:23:08 -08:00
Jared Boone
9856ea3d14 Changes due to CGU header API changes. 2013-11-15 11:41:20 -08:00
Jared Boone
06da7fd83a Reduce drive strength from clock generator (Si5351C) to first mixer (RFFC5072). This reduces every-50MHz spurs in RX by 10 to 15dB. 2013-09-22 11:54:37 -07:00
Jared Boone
314b3cdc7b Don't put MAX2837 into shutdown mode -- powering up takes a bit too long (500us for PLL to stabilize). Will need to revisit, because the MAX2837 chews up significant current (35 to 45mA) when not in shutdown. 
Remove excess calls to max2837_start() and max2837_stop().
 2013-09-22 11:52:45 -07:00
Jared Boone
b4f883595f Remove MAX2837_FREQ_NOMINAL_MHZ #define -- it must be updated now that IF is adjustable. So I pushed the calculation directly into the two places it was used. 2013-09-21 20:27:27 -07:00
Jared Boone
6901107c7f Adjust Makefile_inc.mk to serve both M0 and M4 targets through the LPC43XX_TARGET variable. 2013-09-20 20:04:28 -07:00
Jared Boone
43596e07c5 Break off a chunk of local RAM to serve the M0 processor. 2013-09-20 20:03:24 -07:00