Sojus07/hackrf
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76 Commits

Author SHA1 Message Date
Michael Ossmann
9276b9e89a moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it 2013-05-18 09:48:37 -06:00
TitanMKD
294e958472 sgpio_if (top.vhd) CPLD VHDL fix for IQ/aliasing problems for ADC. (cpldjtagprog => sgpio_if_xsvf.h updated to rebuild). 
usb_performance.c SGPIO IQ fix for ADC (QI->IQ) for new CPLD (use usb_performance_rom_to_ram version else there is some packet lost even at 10Mhz sampling rate => make -f Makefile_rom_to_ram.)
 2013-04-04 19:43:30 +02:00
TitanMKD
fa47f8af8c Fix for IQ problem for ADC: 
RX samples are ordered I0,Q1,I1,Q2,I2,... where they should be I0,Q0,I1,Q1,I2,Q2,...
This fix also alias/ghost problems to be confirmed on other boards/more tests...
Drawback now IQ is QI, will be fixed/swapped in LPC4330 SGPIO code.
 2013-04-04 00:55:51 +02:00
Jared Boone
672e37d040 Added .jed (programmer file) so we can build SVF or XSVF from the bitstream as needed. 
Updated SVF due to "changed" .jed.
Added XSVF for future in-system programming of CPLD.
 2013-02-14 12:13:33 -08:00
TitanMKD
29716c322f Merge branch 'master' of git://github.com/mossmann/hackrf 2012-07-27 19:52:38 +02:00
Jared Boone
4878be8213 New .svf to reflect slew rate and IO standard changes in prior commits. 
Changed name of .svf file to "default.svf" to match what ISE iMPACT wants to write out from "One Step SVF" (a.k.a. "Expresssvf").
 2012-07-24 13:27:19 -07:00
Jared Boone
5ab31b84e0 Remove FAST attribute from all CPLD I/O, since it changes slew rate by less than 1ns -- not enough to be important at 20MHz or so. Will re-examine later, if we try to push bus speed higher on the final board rev. 2012-07-24 12:48:08 -07:00
Jared Boone
18587e3732 Change all IO on CPLD to LVCMOS33 until we make the move to 1V8 supplies on the MAX5864 and Si5351C. 2012-07-24 12:45:46 -07:00
TitanMKD
a54da3fb89 Update of readme 2012-07-20 19:12:32 +02:00
Jared Boone
892f4c1eea Added link to Dangerous Prototypes information on how to switch buffers in Bus Blaster v2. 2012-07-19 16:50:58 -07:00
Jared Boone
6121294550 Moved BSDL requirement to "program" requirements. 2012-07-19 16:48:09 -07:00
TitanMKD
1fa097c954 Added JellyBean final board with pins name. 2012-07-15 12:47:30 +02:00
TitanMKD
724249b227 Adding JellyBean Board PCB & Schematic as PDF. 2012-07-15 12:46:14 +02:00
Jared Boone
64656d1e92 SGPIO passthrough CPLD project, for TitanMKD's testing. 2012-07-02 11:30:44 -07:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
d68036f79d Eliminate ill-conceived HOST_CLK from CPLD. 
Rearrange clocks to not use AC-coupled CLK1 from Si5351C.
Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2.
Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.
 2012-06-14 19:08:20 -07:00
Jared Boone
9c50b7de26 Updated SVF from committed project files. 2012-06-09 22:34:32 -07:00
Jared Boone
89314d40d6 Added Bus Blaster programming script. Added README explaining project contents and programming process. 2012-06-09 22:34:01 -07:00
Jared Boone
07b6f81a6c Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD. 2012-06-09 22:02:45 -07:00
TitanMKD
ba1880799a JellyBean TSP62410 computation theory for output voltage. 2012-05-29 23:11:14 +02:00
TitanMKD
a27210c034 Added JellyBean Pin to be used with NXP http://www.lpcware.com/content/nxpfile/lpc43xx-pin-mux-tool 2012-05-29 23:08:50 +02:00
TitanMKD
ba14f7e539 Fix jellybean_BOM.ods with 3.3V fix. 2012-05-29 23:05:28 +02:00
TitanMKD
71879fc05f JellyBean BOM with DigiKey Part Number 2012-05-28 11:41:41 +02:00
Michael Ossmann
4d90cd6d0a big bom update 2012-04-16 16:29:46 -06:00
Michael Ossmann
4e92238470 gerber options 2012-04-16 09:33:39 -06:00
Michael Ossmann
d1420be69e silkscreen 2012-04-16 09:31:45 -06:00
Michael Ossmann
10da64fc19 flipped boot control headers around 2012-04-16 08:49:12 -06:00
Michael Ossmann
f149b3485c pinned down some zones that were flapping in the breeze 2012-04-15 23:57:32 -06:00
Michael Ossmann
93ac88aa92 finished tracks 2012-04-15 23:41:26 -06:00
Michael Ossmann
edaf103f05 finalized pcb edges 2012-04-15 22:26:39 -06:00
Michael Ossmann
7ebfccba89 more tracks 2012-04-15 21:59:14 -06:00
Michael Ossmann
8835b89201 P9, P12 tracks 2012-04-15 18:09:37 -06:00
Michael Ossmann
819547fa9e LPC JTAG tracks 2012-04-15 17:21:08 -06:00
Michael Ossmann
3fa0e48466 USB, regulator tracks 2012-04-15 17:09:50 -06:00
Michael Ossmann
5369d87fe7 CPLD tracks 2012-04-15 16:16:23 -06:00
Michael Ossmann
9dd9d3c9ec P13 tracks 2012-04-15 11:48:41 -06:00
Michael Ossmann
4e2e5a765b improved regulator placement 2012-04-15 11:19:39 -06:00
Michael Ossmann
d3ccd95641 placed a bunch of passives 2012-04-15 10:19:38 -06:00
Michael Ossmann
4ba3e7b911 fixed VCCIO1 caps 2012-04-15 09:43:46 -06:00
Michael Ossmann
e5ed28dafb more positions 2012-04-15 01:15:23 -06:00
Michael Ossmann
f1fb3abbaf very rough positions 2012-04-15 01:00:32 -06:00
Michael Ossmann
b463ddd7fb modules on layout 2012-04-15 00:21:52 -06:00
Michael Ossmann
947fcb9776 module selection 2012-04-15 00:12:49 -06:00
Michael Ossmann
dd3ad76a79 rearranged USB LEDs for easier experimentation 2012-04-12 23:16:33 -06:00
Michael Ossmann
949b0833d1 fixed some things Jared noticed 2012-04-12 22:45:36 -06:00
Michael Ossmann
f7ab0e7b9f some BOM details 2012-04-10 08:41:40 -06:00
Michael Ossmann
67e4518b28 cosmetic cleanup 2012-04-09 23:44:04 -06:00
Michael Ossmann
3d5c577403 annotation 2012-04-09 23:35:13 -06:00
Michael Ossmann
a7debf80c3 VBUS voltage divider per errata sheet 2012-04-09 23:27:51 -06:00
Michael Ossmann
2925906ded indicator LEDs 2012-04-09 23:22:06 -06:00