SGPIO passthrough CPLD project, for TitanMKD's testing.
This commit is contained in:
Jared Boone
33
hardware/jellybean/sgpio_if_passthrough/README.md
Normal file
33
hardware/jellybean/sgpio_if_passthrough/README.md
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CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either
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as all inputs or all outputs.
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Requirements
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============
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To build this VHDL project and produce an SVF file for flashing the CPLD:
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* Xilinx WebPACK 13.4 for Windows or Linux.
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* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
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in the "Device Models" Support Resources section of the CoolRunner-II
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Product Support & Documentation page. Only one file from the BSDL package is
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required, and the "program" script below expects it to be at the relative
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path "bsdl/xc2c/xc2c64.bsd".
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To program the SVF file into the CPLD:
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* Dangerous Prototypes Bus Blaster v2:
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* Configured with JTAGKey buffers.
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* Connected to CPLD JTAG signals on Jellybean.
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* urJTAG built with libftdi support.
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To Program
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==========
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./program
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...which connects to the Bus Blaster interface 0, sets the BSDL directory,
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detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf
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file to the CPLD.
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10
hardware/jellybean/sgpio_if_passthrough/program
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hardware/jellybean/sgpio_if_passthrough/program
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#!/bin/sh
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echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2
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jtag <<COMMANDSEND
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cable jtagkey vid=0x0403 pid=0x6010 interface=0 driver=ftdi-mpsse
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bsdl path bsdl/xc2c
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detect
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svf sgpio_if_passthrough.svf progress stop
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COMMANDSEND
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2079
hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.svf
Executable file
2079
hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.svf
Executable file
File diff suppressed because it is too large
Load Diff
242
hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.xise
Executable file
242
hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.xise
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@ -0,0 +1,242 @@
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||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|top_tb|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="sgpio_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-29T12:49:49" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8998E598855F452AB5BAE34A005D4FD5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
89
hardware/jellybean/sgpio_if_passthrough/top.ucf
Executable file
89
hardware/jellybean/sgpio_if_passthrough/top.ucf
Executable file
@ -0,0 +1,89 @@
|
||||
#
|
||||
# Copyright 2012 Jared Boone
|
||||
#
|
||||
# This file is part of HackRF.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
|
||||
NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
|
||||
#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18;
|
||||
|
||||
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
|
||||
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
|
||||
|
||||
NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18;
|
||||
|
||||
NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18;
|
||||
|
||||
NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18;
|
||||
NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18;
|
||||
|
||||
NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33;
|
||||
|
||||
NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33;
|
||||
NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33;
|
||||
60
hardware/jellybean/sgpio_if_passthrough/top.vhd
Executable file
60
hardware/jellybean/sgpio_if_passthrough/top.vhd
Executable file
@ -0,0 +1,60 @@
|
||||
--
|
||||
-- Copyright 2012 Jared Boone
|
||||
--
|
||||
-- This file is part of HackRF.
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2, or (at your option)
|
||||
-- any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; see the file COPYING. If not, write to
|
||||
-- the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
-- Boston, MA 02110-1301, USA.
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
entity top is
|
||||
Port(
|
||||
SGPIO : inout std_logic_vector(15 downto 0);
|
||||
|
||||
DA : in std_logic_vector(7 downto 0);
|
||||
DD : out std_logic_vector(9 downto 0);
|
||||
|
||||
CODEC_CLK : in std_logic;
|
||||
CODEC_X2_CLK : in std_logic;
|
||||
|
||||
B1AUX : in std_logic_vector(16 downto 9);
|
||||
B2AUX : inout std_logic_vector(16 downto 1)
|
||||
);
|
||||
|
||||
end top;
|
||||
|
||||
architecture Behavioral of top is
|
||||
type transfer_direction is (to_sgpio, from_sgpio);
|
||||
signal transfer_direction_i : transfer_direction;
|
||||
|
||||
begin
|
||||
|
||||
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
|
||||
else from_sgpio;
|
||||
|
||||
DD <= (DD'high => '1', others => '0');
|
||||
|
||||
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
|
||||
else (others => 'Z');
|
||||
|
||||
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
|
||||
else (others => 'Z');
|
||||
|
||||
end Behavioral;
|
||||
Reference in New Issue
Block a user