For RX, this replaces received samples with an 8-bit incrementing counter.
This allows for identification of any dropped or repeated samples across the
SGPIO interface.
For TX, this compares transmitted samples against another 8-bit incrementing
counter, and raises pin B2AUX1 if they don't match. This should be used with
a tool on the host-side that transmits a matching counter.
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady.
In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.
=======================================
This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**
> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages
Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
```
$ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS
Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output
Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.
More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)
[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
Associating timing specification groups on the NET declarations.
Updated setup/hold constraints -- old constraints were incomplete and possibly incorrect, though I'm still not *positive*.
