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SGPIO: Add CPLD RX Q channel inversion, API to control.

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This commit is contained in:
Jared Boone
2014-08-04 14:20:42 -07:00
parent 0ab6a92ae6
commit 422173a5f7
4 changed files with 21 additions and 2 deletions
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12
firmware/common/sgpio.c
View File

@ -43,13 +43,15 @@ void sgpio_configure_pin_functions() {
scu_pinmux(SCU_PINMUX_SGPIO9, SCU_GPIO_FAST | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_SGPIO10, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO11, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION6);
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0); /* GPIO0[13] */
scu_pinmux(SCU_PINMUX_SGPIO13, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */
scu_pinmux(SCU_PINMUX_SGPIO14, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[13] */
scu_pinmux(SCU_PINMUX_SGPIO15, SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[14] */
sgpio_cpld_stream_rx_set_decimation(1);
sgpio_cpld_stream_rx_set_q_invert(0);
GPIO_DIR(GPIO0) |= GPIOPIN13;
GPIO_DIR(GPIO5) |= GPIOPIN14 | GPIOPIN13 | GPIOPIN12;
}
@ -300,3 +302,11 @@ bool sgpio_cpld_stream_rx_set_decimation(const uint_fast8_t n) {
return (skip_n < 8);
}
void sgpio_cpld_stream_rx_set_q_invert(const uint_fast8_t invert) {
if( invert ) {
GPIO_SET(GPIO0) = GPIOPIN13;
} else {
GPIO_CLR(GPIO0) = GPIOPIN13;
}
}

1
firmware/common/sgpio.h
View File

@ -42,5 +42,6 @@ void sgpio_cpld_stream_disable();
bool sgpio_cpld_stream_is_enabled();
bool sgpio_cpld_stream_rx_set_decimation(const uint_fast8_t n);
void sgpio_cpld_stream_rx_set_q_invert(const uint_fast8_t invert);
#endif//__SGPIO_H__

1
firmware/cpld/sgpio_if/top.ucf
View File

@ -59,6 +59,7 @@ NET "HOST_DATA<0>" LOC="89" |IOSTANDARD=LVCMOS33 | SLEW=SLOW | TNM=to_host;
NET "HOST_DECIM_SEL<2>" LOC="78" |IOSTANDARD=LVCMOS33;
NET "HOST_DECIM_SEL<1>" LOC="81" |IOSTANDARD=LVCMOS33;
NET "HOST_DECIM_SEL<0>" LOC="90" |IOSTANDARD=LVCMOS33;
NET "HOST_Q_INVERT" LOC="70" |IOSTANDARD=LVCMOS33;
TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";

9
firmware/cpld/sgpio_if/top.vhd
View File

@ -33,6 +33,7 @@ entity top is
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
@ -62,6 +63,9 @@ architecture Behavioral of top is
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal q_invert_mask : std_logic_vector(7 downto 0);
begin
@ -113,6 +117,9 @@ begin
end if;
end process;
q_invert <= HOST_Q_INVERT;
q_invert_mask <= X"80" when q_invert = '1' else X"7f";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
@ -121,7 +128,7 @@ begin
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"7f";
data_to_host_o <= adc_data_i xor q_invert_mask;
end if;
end if;
end process;