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Fix CPLD constraint to assume SGPIO frequency of 40MHz, not 20MHz.

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Jared Boone
2013-09-11 16:21:16 -07:00
parent 5a7b927db6
commit e9236e50c2
1 changed files with 1 additions and 1 deletions
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firmware/cpld/sgpio_if/top.ucf
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@ -23,7 +23,7 @@ NET "CODEC_X2_CLK" LOC="27" |IOSTANDARD=LVCMOS33;
#NET "GCLK0" LOC="22" |IOSTANDARD=LVCMOS33;
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns;
NET "DA<7>" LOC="35" |IOSTANDARD=LVCMOS33;
NET "DA<6>" LOC="36" |IOSTANDARD=LVCMOS33;