Jared Boone
ad403fb370
CPLD: Add TX Q invert mechanism.
2014-08-16 17:15:13 -07:00
Jared Boone
8e387e5489
CPLD: Update bitstream files with RX Q channel flip.
2014-08-11 13:02:14 -07:00
Jared Boone
422173a5f7
SGPIO: Add CPLD RX Q channel inversion, API to control.
2014-08-11 13:02:02 -07:00
Michael Ossmann
6bc917ae26
cpld/README
2014-04-24 10:42:25 -06:00
Jared Boone
572f2285f2
Let Xilinx ISE update some unimportant project file header stuff.
2014-01-11 15:17:47 -08:00
Jared Boone
19f285288c
Reset decimator sample count when host_data_enable is 0, so that sample stream starts with a consistent phase. May not be particularly important, but feels cleaner this way...
2014-01-11 15:17:39 -08:00
Jared Boone
3bf6573dc6
Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
...
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
2013-11-19 19:52:06 -08:00
Jared Boone
24a8e2bdb5
Remove CPLD SVF file, as it's not used by anybody (as far as I know).
2013-11-19 19:45:36 -08:00
Jared Boone
d006ec769c
Updated CPLD bitstream with two's complement I/O and sample ordering fix.
2013-11-16 13:41:54 -08:00
Jared Boone
7ef9c1e932
Slow down edges of data lines coming from CPLD.
2013-11-16 13:31:19 -08:00
Jared Boone
147f47a3f5
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
...
Do conversion from unsigned to two's-compliment inside FPGA.
2013-11-16 13:29:00 -08:00
Jared Boone
0a46aae5b9
Convert from unsigned to two's complement inside CPLD. TODO: This requires changes to gr-osmosdr and software that uses hackrf_transfer files directly.
2013-09-16 14:59:14 -07:00
Jared Boone
7075cc6c1c
More constraints clean-up:
...
Associating timing specification groups on the NET declarations.
Updated setup/hold constraints -- old constraints were incomplete and possibly incorrect, though I'm still not *positive*.
2013-09-11 16:55:14 -07:00
Jared Boone
d628e2d09c
Add CODEC_CLK to adc_data constraint group.
2013-09-11 16:22:39 -07:00
Jared Boone
e9236e50c2
Fix CPLD constraint to assume SGPIO frequency of 40MHz, not 20MHz.
2013-09-11 16:21:16 -07:00
Jared Boone
5a7b927db6
Change line endings in CPLD user constraints file license header to match the rest of the file.
2013-09-11 16:20:43 -07:00
Jared Boone
d7e2a8d133
Added note on generating XSVF inside Xilinx tools.
2013-09-11 15:54:17 -07:00
Michael Ossmann
9276b9e89a
moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it
2013-05-18 09:48:37 -06:00
