Marco Bartolucci
fa6bde951c
Added CPLD-based synchronization
...
This is a proof of concept and it's still very crude
For more info read (http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf )
2017-02-17 13:58:55 +01:00
Jared Boone
a380713fdd
CPLD: Separate RX and TX invert, fix TX invert sense.
2014-08-20 08:38:27 -07:00
Jared Boone
b2f92665ea
CPLD: Fix whitespace.
2014-08-20 08:22:47 -07:00
Jared Boone
ad403fb370
CPLD: Add TX Q invert mechanism.
2014-08-16 17:15:13 -07:00
Jared Boone
422173a5f7
SGPIO: Add CPLD RX Q channel inversion, API to control.
2014-08-11 13:02:02 -07:00
Jared Boone
19f285288c
Reset decimator sample count when host_data_enable is 0, so that sample stream starts with a consistent phase. May not be particularly important, but feels cleaner this way...
2014-01-11 15:17:39 -08:00
Jared Boone
3bf6573dc6
Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
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Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
2013-11-19 19:52:06 -08:00
Jared Boone
147f47a3f5
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
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Do conversion from unsigned to two's-compliment inside FPGA.
2013-11-16 13:29:00 -08:00
Jared Boone
0a46aae5b9
Convert from unsigned to two's complement inside CPLD. TODO: This requires changes to gr-osmosdr and software that uses hackrf_transfer files directly.
2013-09-16 14:59:14 -07:00
Jared Boone
7075cc6c1c
More constraints clean-up:
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Associating timing specification groups on the NET declarations.
Updated setup/hold constraints -- old constraints were incomplete and possibly incorrect, though I'm still not *positive*.
2013-09-11 16:55:14 -07:00
Michael Ossmann
9276b9e89a
moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it
2013-05-18 09:48:37 -06:00
