133 lines
4.0 KiB
VHDL
Executable File
133 lines
4.0 KiB
VHDL
Executable File
--
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-- Copyright 2012 Jared Boone
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-- Copyright 2013 Benjamin Vernoux
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--
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-- This file is part of HackRF.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; see the file COPYING. If not, write to
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-- the Free Software Foundation, Inc., 51 Franklin Street,
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-- Boston, MA 02110-1301, USA.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity top is
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Port(
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HOST_DATA : inout std_logic_vector(7 downto 0);
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HOST_CAPTURE : out std_logic;
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HOST_DISABLE : in std_logic;
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HOST_DIRECTION : in std_logic;
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DA : in std_logic_vector(7 downto 0);
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DD : out std_logic_vector(9 downto 0);
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CODEC_CLK : in std_logic;
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CODEC_X2_CLK : in std_logic;
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B1AUX : inout std_logic_vector(16 downto 9);
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B2AUX : inout std_logic_vector(16 downto 1)
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);
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end top;
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architecture Behavioral of top is
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signal codec_clk_i : std_logic;
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signal adc_data_i : std_logic_vector(7 downto 0);
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signal dac_data_o : std_logic_vector(9 downto 0);
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signal host_clk_i : std_logic;
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type transfer_direction is (from_adc, to_dac);
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signal transfer_direction_i : transfer_direction;
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signal host_data_enable_i : std_logic;
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signal host_data_capture_o : std_logic;
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signal data_from_host_i : std_logic_vector(7 downto 0);
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signal data_to_host_o : std_logic_vector(7 downto 0);
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begin
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B1AUX <= (others => '0');
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B2AUX <= (others => '0');
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------------------------------------------------
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-- Codec interface
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adc_data_i <= DA(7 downto 0);
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DD(9 downto 0) <= dac_data_o;
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------------------------------------------------
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-- Clocks
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codec_clk_i <= CODEC_CLK;
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BUFG_host : BUFG
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port map (
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O => host_clk_i,
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I => CODEC_X2_CLK
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);
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------------------------------------------------
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-- SGPIO interface
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HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
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else (others => 'Z');
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data_from_host_i <= HOST_DATA;
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HOST_CAPTURE <= host_data_capture_o;
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host_data_enable_i <= not HOST_DISABLE;
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transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
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else from_adc;
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------------------------------------------------
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process(host_clk_i)
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begin
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if rising_edge(host_clk_i) then
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data_to_host_o <= adc_data_i;
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end if;
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end process;
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process(host_clk_i)
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begin
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if rising_edge(host_clk_i) then
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if transfer_direction_i = to_dac then
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dac_data_o <= data_from_host_i & "00";
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else
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dac_data_o <= (dac_data_o'high => '1', others => '0');
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end if;
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end if;
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end process;
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process(host_clk_i, codec_clk_i)
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begin
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if rising_edge(host_clk_i) then
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if transfer_direction_i = to_dac then
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if codec_clk_i = '1' then
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host_data_capture_o <= host_data_enable_i;
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end if;
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else
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if codec_clk_i = '0' then
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host_data_capture_o <= host_data_enable_i;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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