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Author SHA1 Message Date
Michael Ossmann
9535249efc forgot to redo zones 2012-06-21 19:11:56 -06:00
Michael Ossmann
10133bdf27 redid highpass filter module now that I understand the drawing in the datasheet 2012-06-21 19:10:58 -06:00
Michael Ossmann
e232f7df20 flipped U8 to make more sense in the schematic 2012-06-21 18:56:16 -06:00
Michael Ossmann
c9444582b2 fixed LP0603 pinout, footprint 2012-06-21 18:48:31 -06:00
Michael Ossmann
5207489527 disconnected pin 5 per B0310J50100AHF datasheet 2012-06-21 12:06:40 -06:00
Michael Ossmann
69935ee88c minor cleanup 2012-06-21 11:46:46 -06:00
Michael Ossmann
7de081c7d5 Bubblegum redesign assuming TX_BALUN and RX_BALUN can operate from 10 MHz to 6 GHz 2012-06-21 00:15:04 -06:00
Michael Ossmann
0a5fed5933 tied unused logic input to VCC 2012-06-20 15:14:42 -06:00
Michael Ossmann
0277159ce5 tied unused logic input to VCC 2012-06-20 13:56:51 -06:00
Michael Ossmann
2f5b4fb778 updated layout for switch logic bug fix 2012-06-20 00:08:12 -06:00
Michael Ossmann
2a9502cb50 fixed more switch logic bugs 2012-06-19 23:51:57 -06:00
Michael Ossmann
81f840e623 finished first pass at schematic for bubblegum, an alternative wideband front end 2012-06-19 17:05:41 -06:00
Michael Ossmann
3d7d80c14a reworked layout to fix switch logic bugs 2012-06-19 12:23:53 -06:00
Michael Ossmann
c7aeb2007f fixed PVQFN-14 modules for logic ICs (pins were numbered incorrectly) 2012-06-19 10:48:42 -06:00
Michael Ossmann
53389064f1 fixed switch logic errors in schematic 2012-06-18 21:35:13 -06:00
Michael Ossmann
ba909c0fe5 MAX2837 TXVGA register bug fix 2012-06-18 17:32:23 -06:00
Michael Ossmann
a65186f83c Merge pull request #11 from jboone/master 
Lots of stuff related to getting TX data through the CPLD and DAC, intact.
 2012-06-18 15:23:38 -07:00
Jared Boone
72e3dc1e21 TX sample generation loop that outputs an eight-sample sine wave. (1.25MHz assuming 10MHz codec clock.) 2012-06-15 16:20:46 -07:00
Jared Boone
bab6ec5fef Move buffer allocation to before enabling CPLD I/O, so as not to mess up I/Q synchronization. 2012-06-15 16:16:05 -07:00
Jared Boone
e32a60495a Change initial TX output data to the neutral value (0x80). 2012-06-15 16:14:58 -07:00
Jared Boone
59a5b92300 Correct CPLD JTAG pin release code to properly tri-state the pins. 2012-06-15 16:13:17 -07:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
18d09d2ae2 Renamed incorrectly-named Wiki image. 2012-06-15 15:17:57 -07:00
Jared Boone
f0bf6dbf97 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-06-15 15:11:16 -07:00
Jared Boone
52b665e16c Pictures of SGPIO changes made to improve CPLD/SGPIO clocking. 2012-06-15 15:08:49 -07:00
Michael Ossmann
10e20fbce2 cut out serial test and do some actual mixing 2012-06-14 22:00:27 -06:00
Jared Boone
d68036f79d Eliminate ill-conceived HOST_CLK from CPLD. 
Rearrange clocks to not use AC-coupled CLK1 from Si5351C.
Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2.
Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.
 2012-06-14 19:08:20 -07:00
Michael Ossmann
b0ebd75188 two-clocks-while-ENX-high fix for write operations, various example PLL configs 2012-06-14 19:52:45 -06:00
Jared Boone
f53818a46f Additional calls to initialize SSP1, considering changes I committed minutes earlier. 2012-06-14 13:09:02 -07:00
Jared Boone
570efc1361 Added max2837_rx() function. 2012-06-14 13:06:48 -07:00
Jared Boone
f08fc3bb51 Pulled SSP1 configuration for MAX2837 into hackrf_core. Added SSP1 configuration for MAX5864. Added #defines for manipulating CS of both MAX parts. Changed a couple of #define names to be consistent with other names. Added explicit manipulation of MAX2837 CS via GPIO. 2012-06-14 13:06:10 -07:00
Jared Boone
74ad447ec7 More idiotic editor formatting fixup. 2012-06-14 11:48:07 -07:00
Michael Ossmann
06b63d9936 added two clocks while ENX high to get RFFC5071 serial reads to work (thanks, Jared!) 2012-06-14 12:42:51 -06:00
Jared Boone
388cad86de Code to capture ADC data into a buffer using a tight loop on the M4. 2012-06-14 11:31:11 -07:00
Jared Boone
878936645d Corrected my correction of my misunderstanding of how SGPIO_CTRL_ENABLE works. Turns out I *can* immediately disable a slice using ENABLE. If I want to synchronously disable a slice, I do it via DISABLE. And if I want to screw up my code, I (unwittingly) set all slices to synchronously disable, then configure SGPIO and watch my slices run once and stop. :-( All better now. 2012-06-14 11:30:03 -07:00
Jared Boone
ef46b9b3b6 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-06-14 10:01:35 -07:00
Michael Ossmann
2c76cc9bd2 fixed pinout in README 2012-06-14 10:46:55 -06:00
Michael Ossmann
68f9a1c6e4 fixed inconsistent naming of mixer pins 2012-06-14 10:44:22 -06:00
Michael Ossmann
0075099969 mixertx: tests RFFC5071/Lollipop 2012-06-14 10:40:37 -06:00
Michael Ossmann
a1e2549ae1 troubleshooting RFFC5071 serial 2012-06-14 10:36:38 -06:00
Jared Boone
3c35e39e55 Clean up SGPIO TX code a little bit. 2012-06-13 22:00:37 -07:00
Jared Boone
b5ec859eaf Remove comment of dead code. 2012-06-13 22:00:11 -07:00
Jared Boone
17446f6295 Add RX test, which receives data into a single slice. 2012-06-13 21:58:47 -07:00
Jared Boone
b7a46af009 I was misusing SGPIO_CTRL_ENABLE. Instead, use SGPIO_CTRL_DISABLE to disable slices. 2012-06-13 21:54:48 -07:00
Michael Ossmann
b9cde55f8c initial RFFC5071 support 2012-06-13 21:28:46 -06:00
Michael Ossmann
e71163b44a noting discrepancy between implementations 2012-06-13 21:27:14 -06:00
Michael Ossmann
b54ec7e0ab Merge branch 'master' of github.com:mossmann/hackrf 2012-06-13 21:23:47 -06:00
Michael Ossmann
25c3f6729d Merge branch 'jboone-master' 2012-06-13 21:23:10 -06:00
Michael Ossmann
ad080a355a pull request #10, resolved conflicts 2012-06-13 21:21:34 -06:00
Michael Ossmann
10cebd1f83 RFFC5071 pin defs 2012-06-13 21:08:07 -06:00