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105 Commits

Author SHA1 Message Date
Jared Boone
9a8e5dcdf0 Flip sense of capture clock on SGPIO, which seems to solve the RX data corruption issues. TODO: I wish I had more than empirical evidence that this fix is correct... 2012-07-24 13:31:57 -07:00
Jared Boone
c8c0028d27 Moved CGU peripheral and APB1 base clock configurations to before SSP1 configuration. 2012-07-24 13:29:54 -07:00
Jared Boone
3593bee128 Corrected typo regarding SGPIO external clock configuration. 2012-07-24 13:29:03 -07:00
Michael Ossmann
fea87d8de5 sgpio-rx test firmware 2012-07-23 15:35:44 -06:00
Jared Boone
9f334fc5f0 Simple support for MAX5864 configuration via SPI. 2012-07-19 14:57:06 -07:00
TitanMKD
fab51038c0 SGPIO Test with CPLD passthrough mode => work in progress because I have some hardware issues on my board. 
For details on Hardware issues see Test_SGPIO0_to15.pdf or Test_SGPIO0_to15.ods
 2012-07-15 18:17:27 +02:00
Michael Ossmann
a784812100 updated require connections 2012-06-25 23:36:09 -06:00
TitanMKD
988b3e3a49 Fixed simple systick example 2012-06-25 22:45:18 +02:00
TitanMKD
bb12d3f601 Example removed and replaced by startup_systick_perfo_rom_to_ram 2012-06-25 22:34:29 +02:00
TitanMKD
53c7fcf768 * Fixed linker script form SPIFI and RAM execution. 
* Added performance checks and results on SPIFI & SRAM code execution.
 2012-06-25 22:15:10 +02:00
TitanMKD
dfb38a5a59 Fix asm macro 2012-06-25 22:02:55 +02:00
Jared Boone
2e16f51252 Python program to verify logic on the Lollipop board. 2012-06-19 23:09:42 -07:00
Michael Ossmann
ba909c0fe5 MAX2837 TXVGA register bug fix 2012-06-18 17:32:23 -06:00
Jared Boone
72e3dc1e21 TX sample generation loop that outputs an eight-sample sine wave. (1.25MHz assuming 10MHz codec clock.) 2012-06-15 16:20:46 -07:00
Jared Boone
bab6ec5fef Move buffer allocation to before enabling CPLD I/O, so as not to mess up I/Q synchronization. 2012-06-15 16:16:05 -07:00
Jared Boone
e32a60495a Change initial TX output data to the neutral value (0x80). 2012-06-15 16:14:58 -07:00
Jared Boone
59a5b92300 Correct CPLD JTAG pin release code to properly tri-state the pins. 2012-06-15 16:13:17 -07:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
f0bf6dbf97 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-06-15 15:11:16 -07:00
Michael Ossmann
10e20fbce2 cut out serial test and do some actual mixing 2012-06-14 22:00:27 -06:00
Michael Ossmann
b0ebd75188 two-clocks-while-ENX-high fix for write operations, various example PLL configs 2012-06-14 19:52:45 -06:00
Jared Boone
f53818a46f Additional calls to initialize SSP1, considering changes I committed minutes earlier. 2012-06-14 13:09:02 -07:00
Jared Boone
570efc1361 Added max2837_rx() function. 2012-06-14 13:06:48 -07:00
Jared Boone
f08fc3bb51 Pulled SSP1 configuration for MAX2837 into hackrf_core. Added SSP1 configuration for MAX5864. Added #defines for manipulating CS of both MAX parts. Changed a couple of #define names to be consistent with other names. Added explicit manipulation of MAX2837 CS via GPIO. 2012-06-14 13:06:10 -07:00
Jared Boone
74ad447ec7 More idiotic editor formatting fixup. 2012-06-14 11:48:07 -07:00
Michael Ossmann
06b63d9936 added two clocks while ENX high to get RFFC5071 serial reads to work (thanks, Jared!) 2012-06-14 12:42:51 -06:00
Jared Boone
388cad86de Code to capture ADC data into a buffer using a tight loop on the M4. 2012-06-14 11:31:11 -07:00
Jared Boone
878936645d Corrected my correction of my misunderstanding of how SGPIO_CTRL_ENABLE works. Turns out I *can* immediately disable a slice using ENABLE. If I want to synchronously disable a slice, I do it via DISABLE. And if I want to screw up my code, I (unwittingly) set all slices to synchronously disable, then configure SGPIO and watch my slices run once and stop. :-( All better now. 2012-06-14 11:30:03 -07:00
Jared Boone
ef46b9b3b6 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-06-14 10:01:35 -07:00
Michael Ossmann
2c76cc9bd2 fixed pinout in README 2012-06-14 10:46:55 -06:00
Michael Ossmann
68f9a1c6e4 fixed inconsistent naming of mixer pins 2012-06-14 10:44:22 -06:00
Michael Ossmann
0075099969 mixertx: tests RFFC5071/Lollipop 2012-06-14 10:40:37 -06:00
Michael Ossmann
a1e2549ae1 troubleshooting RFFC5071 serial 2012-06-14 10:36:38 -06:00
Jared Boone
3c35e39e55 Clean up SGPIO TX code a little bit. 2012-06-13 22:00:37 -07:00
Jared Boone
b5ec859eaf Remove comment of dead code. 2012-06-13 22:00:11 -07:00
Jared Boone
17446f6295 Add RX test, which receives data into a single slice. 2012-06-13 21:58:47 -07:00
Jared Boone
b7a46af009 I was misusing SGPIO_CTRL_ENABLE. Instead, use SGPIO_CTRL_DISABLE to disable slices. 2012-06-13 21:54:48 -07:00
Michael Ossmann
b9cde55f8c initial RFFC5071 support 2012-06-13 21:28:46 -06:00
Michael Ossmann
b54ec7e0ab Merge branch 'master' of github.com:mossmann/hackrf 2012-06-13 21:23:47 -06:00
Michael Ossmann
25c3f6729d Merge branch 'jboone-master' 2012-06-13 21:23:10 -06:00
Michael Ossmann
ad080a355a pull request #10, resolved conflicts 2012-06-13 21:21:34 -06:00
Michael Ossmann
10cebd1f83 RFFC5071 pin defs 2012-06-13 21:08:07 -06:00
Jared Boone
2932bb2bd4 I cocked-up backing out an unwanted change to CFLAGS which created badness in the Makefile_inc.mk file. 2012-06-13 18:13:26 -07:00
Jared Boone
d6cf4ec014 Initial SGPIO implementation. Sends a constant value to each channel of the DAC that can be measured as differential voltages to identify which channel is which. 2012-06-13 18:04:13 -07:00
Jared Boone
61b7b76912 OOPS. Missed changes from clock reconfiguration two commits (and five minutes) ago. 2012-06-13 17:58:14 -07:00
Jared Boone
d99533d112 Added C99 support to CFLAGS. It's been 13 years now... 2012-06-13 17:53:57 -07:00
Jared Boone
02f61f4d64 Added r_div argument to si5351c_configure_multisynth(). Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to CPLD (both inverted and non-inverted). 2012-06-13 17:53:10 -07:00
Jared Boone
ca18d36779 #defines for CPLD JTAG interface on LPC43xx. 2012-06-13 16:47:38 -07:00
Michael Ossmann
bc5218f1e9 Merge pull request #9 from TitanMKD/master 
LPCXpresso LPC43xx Debugger Tutorial
 2012-06-13 16:16:39 -07:00
TitanMKD
8828cf2b24 LPCXpresso IDE Flash/Debug Tutorial for LPC43xx SPIFI 2012-06-14 01:09:04 +02:00