29 Commits

Author SHA1 Message Date
Jared Boone
3932c5694e PortaPack: Add .SVF of current JEDEC bitstream file.
PortaPack build consumes this file to embed the bitstream into the firmware.
2019-01-15 15:31:53 -08:00
Michael Ossmann
fc8fcd8616 added CPLD update requirement to firmware/README
improved cpld/README
fixes #458
2018-02-20 08:18:42 -07:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00
Marco Bartolucci
d47dece3ba Fixed indentation 2017-05-15 11:49:23 +02:00
Marco Bartolucci
808fd9410e Bump to latest version
Merge remote-tracking branch 'upstream/master'
2017-05-05 11:58:43 +02:00
Marco Bartolucci
9d6f2a7e9c Fixed sgpio_if readme 2017-02-17 14:05:33 +01:00
Marco Bartolucci
fa6bde951c Added CPLD-based synchronization
This is a proof of concept and it's still very crude
For more info read (http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-02-17 13:58:55 +01:00
Dominic Spill
a4036eab76 Remove last mentions of Jellybean 2017-02-16 18:03:32 -07:00
Jared Boone
a380713fdd CPLD: Separate RX and TX invert, fix TX invert sense. 2014-08-20 08:38:27 -07:00
Jared Boone
b2f92665ea CPLD: Fix whitespace. 2014-08-20 08:22:47 -07:00
Jared Boone
ad403fb370 CPLD: Add TX Q invert mechanism. 2014-08-16 17:15:13 -07:00
Jared Boone
8e387e5489 CPLD: Update bitstream files with RX Q channel flip. 2014-08-11 13:02:14 -07:00
Jared Boone
422173a5f7 SGPIO: Add CPLD RX Q channel inversion, API to control. 2014-08-11 13:02:02 -07:00
Michael Ossmann
6bc917ae26 cpld/README 2014-04-24 10:42:25 -06:00
Jared Boone
572f2285f2 Let Xilinx ISE update some unimportant project file header stuff. 2014-01-11 15:17:47 -08:00
Jared Boone
19f285288c Reset decimator sample count when host_data_enable is 0, so that sample stream starts with a consistent phase. May not be particularly important, but feels cleaner this way... 2014-01-11 15:17:39 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
2013-11-19 19:52:06 -08:00
Jared Boone
24a8e2bdb5 Remove CPLD SVF file, as it's not used by anybody (as far as I know). 2013-11-19 19:45:36 -08:00
Jared Boone
d006ec769c Updated CPLD bitstream with two's complement I/O and sample ordering fix. 2013-11-16 13:41:54 -08:00
Jared Boone
7ef9c1e932 Slow down edges of data lines coming from CPLD. 2013-11-16 13:31:19 -08:00
Jared Boone
147f47a3f5 Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
2013-11-16 13:29:00 -08:00
Jared Boone
0a46aae5b9 Convert from unsigned to two's complement inside CPLD. TODO: This requires changes to gr-osmosdr and software that uses hackrf_transfer files directly. 2013-09-16 14:59:14 -07:00
Jared Boone
7075cc6c1c More constraints clean-up:
Associating timing specification groups on the NET declarations.
Updated setup/hold constraints -- old constraints were incomplete and possibly incorrect, though I'm still not *positive*.
2013-09-11 16:55:14 -07:00
Jared Boone
d628e2d09c Add CODEC_CLK to adc_data constraint group. 2013-09-11 16:22:39 -07:00
Jared Boone
e9236e50c2 Fix CPLD constraint to assume SGPIO frequency of 40MHz, not 20MHz. 2013-09-11 16:21:16 -07:00
Jared Boone
5a7b927db6 Change line endings in CPLD user constraints file license header to match the rest of the file. 2013-09-11 16:20:43 -07:00
Jared Boone
d7e2a8d133 Added note on generating XSVF inside Xilinx tools. 2013-09-11 15:54:17 -07:00
Michael Ossmann
9276b9e89a moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it 2013-05-18 09:48:37 -06:00