16 Commits

Author SHA1 Message Date
Jared Boone
f22fcd6083 CPLD: Finish fixing up timing re-validation for RX and TX. 2019-01-21 16:19:41 -08:00
Jared Boone
d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
2019-01-18 16:09:14 -08:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00
Marco Bartolucci
d47dece3ba Fixed indentation 2017-05-15 11:49:23 +02:00
Marco Bartolucci
fa6bde951c Added CPLD-based synchronization
This is a proof of concept and it's still very crude
For more info read (http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-02-17 13:58:55 +01:00
Jared Boone
a380713fdd CPLD: Separate RX and TX invert, fix TX invert sense. 2014-08-20 08:38:27 -07:00
Jared Boone
b2f92665ea CPLD: Fix whitespace. 2014-08-20 08:22:47 -07:00
Jared Boone
ad403fb370 CPLD: Add TX Q invert mechanism. 2014-08-16 17:15:13 -07:00
Jared Boone
422173a5f7 SGPIO: Add CPLD RX Q channel inversion, API to control. 2014-08-11 13:02:02 -07:00
Jared Boone
19f285288c Reset decimator sample count when host_data_enable is 0, so that sample stream starts with a consistent phase. May not be particularly important, but feels cleaner this way... 2014-01-11 15:17:39 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
2013-11-19 19:52:06 -08:00
Jared Boone
147f47a3f5 Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
2013-11-16 13:29:00 -08:00
Jared Boone
0a46aae5b9 Convert from unsigned to two's complement inside CPLD. TODO: This requires changes to gr-osmosdr and software that uses hackrf_transfer files directly. 2013-09-16 14:59:14 -07:00
Jared Boone
7075cc6c1c More constraints clean-up:
Associating timing specification groups on the NET declarations.
Updated setup/hold constraints -- old constraints were incomplete and possibly incorrect, though I'm still not *positive*.
2013-09-11 16:55:14 -07:00
Michael Ossmann
9276b9e89a moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it 2013-05-18 09:48:37 -06:00