Jared Boone
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1bec883f80
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Add baseband sampling frequencies useful for 48kHz audio output.
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2013-12-31 20:05:26 -08:00 |
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Jared Boone
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9f2260237b
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Add GPDMA LLI functions to create a loop or one-shot chain of LLIs.
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2013-12-08 18:18:22 -08:00 |
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Jared Boone
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5b59f9cb0a
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Change GPDMA channel clli member to uint32_t, casting to/from gpdma_lli_t and dealing with the multiple fields was driving me crazy.
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2013-12-08 18:16:58 -08:00 |
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Jared Boone
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6185b67008
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Add GPDMA LLI function to enable interrupt after LLI operation is complete.
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2013-12-08 17:49:50 -08:00 |
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Jared Boone
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ca070acad0
|
Expose SGPIO DMA LLI configuration function.
Remove LLI declarations internal to SGPIO DMA module.
Require a start LLI for SGPIO DMA start functions.
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2013-12-08 13:14:26 -08:00 |
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Jared Boone
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ea2ca52301
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Rename SGPIO DMA internal function to match style of public functions.
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2013-12-08 13:07:32 -08:00 |
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Jared Boone
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ac0d50a131
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Remove irrelevant assumption that LLI argument is a pointer to an array.
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2013-12-08 13:06:14 -08:00 |
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Jared Boone
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d2fd5e74c5
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Change SGPIO DMA configuration API from dividing up a buffer's length into M parts to creating a chain of M transfers of size N.
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2013-12-08 13:05:30 -08:00 |
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Jared Boone
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6196fa2810
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Move LLI_COUNT constant out of SGPIO DMA utility functions.
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2013-12-08 12:50:20 -08:00 |
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Jared Boone
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2fab6c40cd
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Extract SGPIO multi_slice configuration argument into an init-time function, so it doesn't need to be passed each time the SGPIO interface direction is changed.
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2013-12-08 12:21:41 -08:00 |
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Jared Boone
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50ec268794
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Bracket SGPIO GPDMA slice configuration with multislice==false test. It only makes sense in single slice mode (until I have a clever idea for doing GPDMA with multiple slices).
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2013-12-08 12:14:00 -08:00 |
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Jared Boone
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809df425c1
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Add SGPIO configuration to support GPDMA interrupts.
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2013-12-08 11:54:50 -08:00 |
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Jared Boone
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45c0a6c31a
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Extract/isolate path details in Makefile_inc.mk.
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2013-12-08 11:33:47 -08:00 |
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Jared Boone
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f51ee2dc61
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Modified ldscripts to more accurately represent LPC4330 hardware.
Moved M0 RAM from local to AHB.
Created separate region for sleep RAM.
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2013-12-07 15:29:50 -08:00 |
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Jared Boone
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34b01d89af
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Add SGPIO DMA configuration code.
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2013-12-07 15:29:14 -08:00 |
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Jared Boone
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3e7ff530d7
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Add GPDMA API. Should go in libopencm3 when it's more fleshed-out.
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2013-12-07 15:28:59 -08:00 |
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Jared Boone
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5468a01a9b
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Forgot to include rf_path.h now that its pin setup is called from hackrf_core.
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2013-11-21 10:23:53 -08:00 |
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Jared Boone
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b285b91e4c
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Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906
Conflicts:
firmware/common/hackrf_core.h
firmware/common/rffc5071.c
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2013-11-20 18:43:40 -08:00 |
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Jared Boone
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62ab69c3d2
|
Giant .gitignore to knock out build files, Xilinx spew, and editor/OS turds.
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2013-11-20 15:51:59 -08:00 |
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Jared Boone
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9db166427f
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Remove I2S pin definitions, since they're too specific for generic/shared HackRF code.
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2013-11-20 15:46:53 -08:00 |
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Jared Boone
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f453e4c377
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Bump libopencm3.
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2013-11-20 15:44:15 -08:00 |
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Jared Boone
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986e4dec93
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Massive rework of Makefile_inc.mk, to support building of heterogeneous (M4+M0) binaries, and easy switching between RAM and SPIFI-bootable builds. Constructive criticism welcome -- I'm sure there's better ways to do this.
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2013-11-20 15:28:28 -08:00 |
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Jared Boone
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02ba23bf68
|
Fix broken sgpio-rx project, broken due to massive changes to how RF path and tuning is done.
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2013-11-20 15:24:50 -08:00 |
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Jared Boone
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893c20e41f
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Fix naming problem with SGPIO test project. This is due to my use of VPATH in Makefile_inc.mk, which I'm starting to regret a little bit...
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2013-11-20 15:24:14 -08:00 |
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Jared Boone
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552dbe4a6d
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Add sgpio.c to C files, now required for pin initialization.
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2013-11-20 15:23:26 -08:00 |
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Jared Boone
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6a03f157ff
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With Makefile RAM/SPIFI option, remove/rework redundant "rom_to_ram" projects.
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2013-11-20 15:21:40 -08:00 |
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Jared Boone
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c365d0a37e
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Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region.
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2013-11-20 15:14:13 -08:00 |
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Jared Boone
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31a55d0e9b
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Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now...
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2013-11-20 15:13:18 -08:00 |
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Jared Boone
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e29ec6b084
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Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files.
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2013-11-20 15:11:54 -08:00 |
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Jared Boone
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91a7ca4983
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Fix return value on SGPIO decimation function.
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2013-11-20 15:08:59 -08:00 |
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Jared Boone
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e3f9e204c1
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Relocate SGPIO pin configuration -- it only needs to be done once.
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2013-11-20 13:22:19 -08:00 |
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Jared Boone
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39276f162c
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Add M0 linker script.
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2013-11-19 19:52:50 -08:00 |
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Jared Boone
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3bf6573dc6
|
Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
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2013-11-19 19:52:06 -08:00 |
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Jared Boone
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24a8e2bdb5
|
Remove CPLD SVF file, as it's not used by anybody (as far as I know).
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2013-11-19 19:45:36 -08:00 |
|
Michael Ossmann
|
5b14636c2c
|
initial firmware support for HackRF One
|
2013-11-19 10:01:26 -07:00 |
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Jared Boone
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967e699815
|
Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values.
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2013-11-17 22:23:08 -08:00 |
|
Michael Ossmann
|
a909ca641c
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moved GCK1 test point
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2013-11-16 21:39:15 -07:00 |
|
Michael Ossmann
|
ca2162da29
|
forgot to save schematic
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2013-11-16 21:26:07 -07:00 |
|
Michael Ossmann
|
95ffc704a1
|
P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28
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2013-11-16 21:22:25 -07:00 |
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Jared Boone
|
d006ec769c
|
Updated CPLD bitstream with two's complement I/O and sample ordering fix.
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2013-11-16 13:41:54 -08:00 |
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Jared Boone
|
89eafaa79a
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Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this.
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2013-11-16 13:32:41 -08:00 |
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Jared Boone
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7ef9c1e932
|
Slow down edges of data lines coming from CPLD.
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2013-11-16 13:31:19 -08:00 |
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Jared Boone
|
147f47a3f5
|
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
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2013-11-16 13:29:00 -08:00 |
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Jared Boone
|
9856ea3d14
|
Changes due to CGU header API changes.
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2013-11-15 11:41:20 -08:00 |
|
Michael Ossmann
|
db3ef109fa
|
forgot to save schematic when adding clock signals to header
|
2013-11-11 20:56:47 -07:00 |
|
Michael Ossmann
|
06f345239b
|
silkscreen tweaks
|
2013-11-11 20:49:57 -07:00 |
|
Michael Ossmann
|
fecc7346b3
|
GND test points
|
2013-11-11 19:25:28 -07:00 |
|
Michael Ossmann
|
a8c2c0b6d1
|
more decoupling caps
|
2013-11-11 19:07:28 -07:00 |
|
Michael Ossmann
|
26104e6735
|
nudged some traces in the RF section
|
2013-11-11 18:48:39 -07:00 |
|
Michael Ossmann
|
c5533b3c96
|
reworked zones so LED signals do not cross power planes
|
2013-11-11 18:04:45 -07:00 |
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