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Merge pull request #126 from jboone/cpld_tx_q_invert_fix

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CPLD TX Q invert fix
This commit is contained in:
Michael Ossmann
2014-08-21 12:11:24 -06:00
parent aec97e7470 a380713fdd
commit dcc070c31f
3 changed files with 52 additions and 50 deletions
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BIN
firmware/cpld/sgpio_if/default.xsvf
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24
firmware/cpld/sgpio_if/top.jed
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@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Sat Aug 16 17:13:17 2014
Date Extracted: Wed Aug 20 08:36:47 2014
QF25812*
QP100*
@ -68,7 +68,7 @@ L001440 110101111111011101111111111111111111111111101111111111111111111111111111
L001520 11110111111110111111110111111111111111111101111111111111111111111111111111111111*
L001600 11010111111110110111111011111111111111111111111111111111111111111111111111111111*
L001680 11111011110111111111111111111111111111111111111111111111111111111111111111111111*
L001760 11111111110111111111111111111111111101111111111111111111111111111111111111111111*
L001760 11111111110111111111111111111111111110111111111111111111111111111111111111111111*
L001840 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001920 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002000 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
@ -232,21 +232,21 @@ L007056 1111111111111111*
L007072 1111111111111111*
Note Block 1 PLA AND array *
L007088 11111111110111111011111111111101011111111111111111111111111111111111111111111111*
L007088 11111111110111110111111111111101011111111111111111111111111111111111111111111111*
L007168 11111101111111111111111111111111101111111111111111111111111111111111111111111111*
L007248 11111111110111111011011111111101111111111111111111111111111111111111111111111111*
L007248 11111111110111110111011111111101111111111111111111111111111111111111111111111111*
L007328 11111101111111111111101111111111111111111111111111111111111111111111111111111111*
L007408 11111111110111111001111111111101111111111111111111111111111111111111111111111111*
L007408 11111111110111110101111111111101111111111111111111111111111111111111111111111111*
L007488 11111101111111111110111111111111111111111111111111111111111111111111111111111111*
L007568 11111111110111111011111111111101111111111101111111111111111111111111111111111111*
L007568 11111111110111110111111111111101111111111101111111111111111111111111111111111111*
L007648 11111101111111111111111111111111111111111110111111111111111111111111111111111111*
L007728 11111111010111111011111111111101111111111111111111111111111111111111111111111111*
L007728 11111111010111110111111111111101111111111111111111111111111111111111111111111111*
L007808 11111101101111111111111111111111111111111111111111111111111111111111111111111111*
L007888 11110111110111111011111111111101111111111111111111111111111111111111111111111111*
L007888 11110111110111110111111111111101111111111111111111111111111111111111111111111111*
L007968 11111001111111111111111111111111111111111111111111111111111111111111111111111111*
L008048 11011111110111111011111111111101111111111111111111111111111111111111111111111111*
L008048 11011111110111110111111111111101111111111111111111111111111111111111111111111111*
L008128 11101101111111111111111111111111111111111111111111111111111111111111111111111111*
L008208 11111111110111111011111111110101111111111111111111111111111111111111111111111111*
L008208 11111111110111110111111111110101111111111111111111111111111111111111111111111111*
L008288 11111101111111111111111111111011111111111111111111111111111111111111111111111111*
L008368 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008448 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
@ -753,5 +753,5 @@ L025810 0*
Note I/O Bank 1 Vcco *
L025811 0*
CFB9B*
AA89
CFB93*
AA7A

78
firmware/cpld/sgpio_if/top.vhd
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@ -21,7 +21,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
@ -31,8 +31,8 @@ entity top is
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
@ -60,12 +60,13 @@ architecture Behavioral of top is
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal q_invert_mask : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
@ -97,39 +98,40 @@ begin
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
q_invert_mask <= X"80" when q_invert = '1' else X"7f";
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor q_invert_mask;
end if;
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
@ -138,7 +140,7 @@ begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor q_invert_mask) & q_invert_mask(0) & q_invert_mask(0);
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;