From b2f92665ead1352624b0ac2b16930499ee95b6d8 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Wed, 20 Aug 2014 08:04:09 -0700 Subject: [PATCH 1/2] CPLD: Fix whitespace. --- firmware/cpld/sgpio_if/top.vhd | 74 +++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/firmware/cpld/sgpio_if/top.vhd b/firmware/cpld/sgpio_if/top.vhd index b93de6cf..a8fca45a 100755 --- a/firmware/cpld/sgpio_if/top.vhd +++ b/firmware/cpld/sgpio_if/top.vhd @@ -21,7 +21,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -use ieee.std_logic_unsigned.all; +use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.vcomponents.all; @@ -31,8 +31,8 @@ entity top is HOST_DATA : inout std_logic_vector(7 downto 0); HOST_CAPTURE : out std_logic; HOST_DISABLE : in std_logic; - HOST_DIRECTION : in std_logic; - HOST_DECIM_SEL : in std_logic_vector(2 downto 0); + HOST_DIRECTION : in std_logic; + HOST_DECIM_SEL : in std_logic_vector(2 downto 0); HOST_Q_INVERT : in std_logic; DA : in std_logic_vector(7 downto 0); @@ -60,12 +60,12 @@ architecture Behavioral of top is signal data_from_host_i : std_logic_vector(7 downto 0); signal data_to_host_o : std_logic_vector(7 downto 0); - signal decimate_count : std_logic_vector(2 downto 0) := "111"; - signal decimate_sel_i : std_logic_vector(2 downto 0); - signal decimate_en : std_logic; - - signal q_invert : std_logic; - signal q_invert_mask : std_logic_vector(7 downto 0); + signal decimate_count : std_logic_vector(2 downto 0) := "111"; + signal decimate_sel_i : std_logic_vector(2 downto 0); + signal decimate_en : std_logic; + + signal q_invert : std_logic; + signal q_invert_mask : std_logic_vector(7 downto 0); begin @@ -97,39 +97,39 @@ begin host_data_enable_i <= not HOST_DISABLE; transfer_direction_i <= to_dac when HOST_DIRECTION = '1' else from_adc; - - decimate_sel_i <= HOST_DECIM_SEL; - - ------------------------------------------------ - - decimate_en <= '1' when decimate_count = "111" else '0'; - - process(host_clk_i) - begin - if rising_edge(host_clk_i) then - if codec_clk_i = '1' then - if decimate_count = "111" or host_data_enable_i = '0' then - decimate_count <= decimate_sel_i; - else - decimate_count <= decimate_count + 1; - end if; - end if; - end if; - end process; - - q_invert <= HOST_Q_INVERT; - q_invert_mask <= X"80" when q_invert = '1' else X"7f"; - + + decimate_sel_i <= HOST_DECIM_SEL; + + ------------------------------------------------ + + decimate_en <= '1' when decimate_count = "111" else '0'; + process(host_clk_i) begin if rising_edge(host_clk_i) then - if codec_clk_i = '1' then - -- I: non-inverted between MAX2837 and MAX5864 + if codec_clk_i = '1' then + if decimate_count = "111" or host_data_enable_i = '0' then + decimate_count <= decimate_sel_i; + else + decimate_count <= decimate_count + 1; + end if; + end if; + end if; + end process; + + q_invert <= HOST_Q_INVERT; + q_invert_mask <= X"80" when q_invert = '1' else X"7f"; + + process(host_clk_i) + begin + if rising_edge(host_clk_i) then + if codec_clk_i = '1' then + -- I: non-inverted between MAX2837 and MAX5864 data_to_host_o <= adc_data_i xor X"80"; else - -- Q: inverted between MAX2837 and MAX5864 - data_to_host_o <= adc_data_i xor q_invert_mask; - end if; + -- Q: inverted between MAX2837 and MAX5864 + data_to_host_o <= adc_data_i xor q_invert_mask; + end if; end if; end process; From a380713fdd444f85ca65e442a374485ef17aa7a2 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Wed, 20 Aug 2014 08:21:06 -0700 Subject: [PATCH 2/2] CPLD: Separate RX and TX invert, fix TX invert sense. --- firmware/cpld/sgpio_if/default.xsvf | Bin 37629 -> 37629 bytes firmware/cpld/sgpio_if/top.jed | 24 ++++++++++++------------ firmware/cpld/sgpio_if/top.vhd | 10 ++++++---- 3 files changed, 18 insertions(+), 16 deletions(-) diff --git a/firmware/cpld/sgpio_if/default.xsvf b/firmware/cpld/sgpio_if/default.xsvf index 9b912c7dc1f17e19a54369346c75dff46fb969b7..1b78dbcffbe8e7ac10505df8f7ced610fe1d4d69 100644 GIT binary patch delta 77 zcmeynl^05W$ct^fc4 diff --git a/firmware/cpld/sgpio_if/top.jed b/firmware/cpld/sgpio_if/top.jed index cf7e4a32..abe1ddf1 100755 --- a/firmware/cpld/sgpio_if/top.jed +++ b/firmware/cpld/sgpio_if/top.jed @@ -1,5 +1,5 @@ Programmer Jedec Bit Map -Date Extracted: Sat Aug 16 17:13:17 2014 +Date Extracted: Wed Aug 20 08:36:47 2014 QF25812* QP100* @@ -68,7 +68,7 @@ L001440 110101111111011101111111111111111111111111101111111111111111111111111111 L001520 11110111111110111111110111111111111111111101111111111111111111111111111111111111* L001600 11010111111110110111111011111111111111111111111111111111111111111111111111111111* L001680 11111011110111111111111111111111111111111111111111111111111111111111111111111111* -L001760 11111111110111111111111111111111111101111111111111111111111111111111111111111111* +L001760 11111111110111111111111111111111111110111111111111111111111111111111111111111111* L001840 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L001920 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L002000 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -232,21 +232,21 @@ L007056 1111111111111111* L007072 1111111111111111* Note Block 1 PLA AND array * -L007088 11111111110111111011111111111101011111111111111111111111111111111111111111111111* +L007088 11111111110111110111111111111101011111111111111111111111111111111111111111111111* L007168 11111101111111111111111111111111101111111111111111111111111111111111111111111111* -L007248 11111111110111111011011111111101111111111111111111111111111111111111111111111111* +L007248 11111111110111110111011111111101111111111111111111111111111111111111111111111111* L007328 11111101111111111111101111111111111111111111111111111111111111111111111111111111* -L007408 11111111110111111001111111111101111111111111111111111111111111111111111111111111* +L007408 11111111110111110101111111111101111111111111111111111111111111111111111111111111* L007488 11111101111111111110111111111111111111111111111111111111111111111111111111111111* -L007568 11111111110111111011111111111101111111111101111111111111111111111111111111111111* +L007568 11111111110111110111111111111101111111111101111111111111111111111111111111111111* L007648 11111101111111111111111111111111111111111110111111111111111111111111111111111111* -L007728 11111111010111111011111111111101111111111111111111111111111111111111111111111111* +L007728 11111111010111110111111111111101111111111111111111111111111111111111111111111111* L007808 11111101101111111111111111111111111111111111111111111111111111111111111111111111* -L007888 11110111110111111011111111111101111111111111111111111111111111111111111111111111* +L007888 11110111110111110111111111111101111111111111111111111111111111111111111111111111* L007968 11111001111111111111111111111111111111111111111111111111111111111111111111111111* -L008048 11011111110111111011111111111101111111111111111111111111111111111111111111111111* +L008048 11011111110111110111111111111101111111111111111111111111111111111111111111111111* L008128 11101101111111111111111111111111111111111111111111111111111111111111111111111111* -L008208 11111111110111111011111111110101111111111111111111111111111111111111111111111111* +L008208 11111111110111110111111111110101111111111111111111111111111111111111111111111111* L008288 11111101111111111111111111111011111111111111111111111111111111111111111111111111* L008368 11111111111111111111111111111111111111111111111111111111111111111111111111111111* L008448 11111111111111111111111111111111111111111111111111111111111111111111111111111111* @@ -753,5 +753,5 @@ L025810 0* Note I/O Bank 1 Vcco * L025811 0* -CFB9B* -AA89 +CFB93* +AA7A diff --git a/firmware/cpld/sgpio_if/top.vhd b/firmware/cpld/sgpio_if/top.vhd index a8fca45a..c74bcd0b 100755 --- a/firmware/cpld/sgpio_if/top.vhd +++ b/firmware/cpld/sgpio_if/top.vhd @@ -65,7 +65,8 @@ architecture Behavioral of top is signal decimate_en : std_logic; signal q_invert : std_logic; - signal q_invert_mask : std_logic_vector(7 downto 0); + signal rx_q_invert_mask : std_logic_vector(7 downto 0); + signal tx_q_invert_mask : std_logic_vector(7 downto 0); begin @@ -118,7 +119,8 @@ begin end process; q_invert <= HOST_Q_INVERT; - q_invert_mask <= X"80" when q_invert = '1' else X"7f"; + rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f"; + tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80"; process(host_clk_i) begin @@ -128,7 +130,7 @@ begin data_to_host_o <= adc_data_i xor X"80"; else -- Q: inverted between MAX2837 and MAX5864 - data_to_host_o <= adc_data_i xor q_invert_mask; + data_to_host_o <= adc_data_i xor rx_q_invert_mask; end if; end if; end process; @@ -138,7 +140,7 @@ begin if rising_edge(host_clk_i) then if transfer_direction_i = to_dac then if codec_clk_i = '1' then - dac_data_o <= (data_from_host_i xor q_invert_mask) & q_invert_mask(0) & q_invert_mask(0); + dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0); else dac_data_o <= (data_from_host_i xor X"80") & "00"; end if;