mounting holes, inner layers

This commit is contained in:
Michael Ossmann
2012-05-19 17:02:45 -06:00
parent a5e33b7cb5
commit 97eb74ddde
6 changed files with 4187 additions and 2219 deletions

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@ -1,4 +1,4 @@
PCBNEW-LibModule-V1 Fri May 18 16:40:43 2012
PCBNEW-LibModule-V1 Sat May 19 16:29:59 2012
# encoding utf-8
$INDEX
GSG-HEADER-1x3
@ -6581,24 +6581,6 @@ Po 9500 -500
Le 33
$EndPAD
$EndMODULE GSG-HEADER-2x20
$MODULE GSG-HOLE-12MIL
Po 0 0 0 15 4FA35846 00000000 ~~
Li GSG-HOLE-12MIL
Kw DEV
Sc 00000000
AR GSG-HOLE-12MIL
Op 0 0 0
T0 0 -1200 400 400 0 100 N V 21 N "GSG-HOLE-12MIL"
T1 0 1100 400 400 0 100 N I 21 N "P***"
$PAD
Sh "" C 2250 2250 0 0 0
Dr 1200 0 0
At STD N 00C0FFFF
Ne 0 ""
Po 0 0
Le 1416511272
$EndPAD
$EndMODULE GSG-HOLE-12MIL
$MODULE GSG-LXES1UBBB1-008
Po 0 0 0 15 4FB67CFC 00000000 ~~
Li GSG-LXES1UBBB1-008
@ -7735,4 +7717,22 @@ Le 24791752
.SolderMask 40
$EndPAD
$EndMODULE GSG-0402
$MODULE GSG-HOLE-12MIL
Po 0 0 0 15 4FB81EE3 00000000 ~~
Li GSG-HOLE-12MIL
Kw DEV
Sc 00000000
AR GSG-HOLE-12MIL
Op 0 0 0
T0 0 -1200 400 400 0 100 N V 21 N "GSG-HOLE-12MIL"
T1 0 1100 400 400 0 100 N I 21 N "P***"
$PAD
Sh "1" C 2250 2250 0 0 0
Dr 1200 0 0
At STD N 00C0FFFF
Ne 0 ""
Po 0 0
Le 1416511272
$EndPAD
$EndMODULE GSG-HOLE-12MIL
$EndLIBRARY

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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Sat May 19 16:05:01 2012
EESchema-LIBRARY Version 2.3 Date: Sat May 19 16:28:34 2012
#encoding utf-8
#
# BALUN
@ -73,6 +73,18 @@ X ~ 2 0 -200 170 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_1
#
DEF ~CONN_1 P 0 30 N N 1 F N
F0 "P" 80 0 40 H V L CNN
F1 "CONN_1" 0 55 30 H I C CNN
DRAW
C 0 0 31 0 1 0 N
P 2 0 1 0 -30 0 -50 0 N
X 1 1 -150 0 100 R 60 60 1 1 P
ENDDRAW
ENDDEF
#
# CONN_2
#
DEF CONN_2 P 0 40 Y N 1 F N

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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Fri May 18 16:44:42 2012
Cmp-Mod V01 Created by CvPCB (2011-06-30 BZR 3033)-stable date = Sat May 19 16:29:17 2012
BeginCmp
TimeStamp = /4FA9C67C;
@ -514,7 +514,7 @@ EndCmp
BeginCmp
TimeStamp = /4FAECD45;
Reference = C74;
ValeurCmp = 1.2nF;
ValeurCmp = 47pF;
IdModule = GSG-0402;
EndCmp
@ -535,7 +535,7 @@ EndCmp
BeginCmp
TimeStamp = /4FB3CC76;
Reference = C77;
ValeurCmp = 1nF;
ValeurCmp = 47pF;
IdModule = GSG-0402;
EndCmp
@ -651,6 +651,34 @@ ValeurCmp = VCC;
IdModule = GSG-HEADER-2x3;
EndCmp
BeginCmp
TimeStamp = /4FB81E54;
Reference = P9;
ValeurCmp = CONN_1;
IdModule = GSG-HOLE-12MIL;
EndCmp
BeginCmp
TimeStamp = /4FB81E53;
Reference = P10;
ValeurCmp = CONN_1;
IdModule = GSG-HOLE-12MIL;
EndCmp
BeginCmp
TimeStamp = /4FB81E51;
Reference = P11;
ValeurCmp = CONN_1;
IdModule = GSG-HOLE-12MIL;
EndCmp
BeginCmp
TimeStamp = /4FB81E45;
Reference = P12;
ValeurCmp = CONN_1;
IdModule = GSG-HOLE-12MIL;
EndCmp
BeginCmp
TimeStamp = /4FAEC850;
Reference = R1;

File diff suppressed because it is too large Load Diff

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sat May 19 16:05:01 2012
EESchema Schematic File Version 2 date Sat May 19 16:28:34 2012
LIBS:power
LIBS:device
LIBS:transistors
@ -45,6 +45,48 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
NoConn ~ 12000 10350
NoConn ~ 11900 10350
NoConn ~ 11800 10350
NoConn ~ 11700 10350
Text Notes 11600 10000 0 40 ~ 0
mounting holes
$Comp
L CONN_1 P9
U 1 1 4FB81E54
P 11700 10200
F 0 "P9" H 11780 10200 40 0000 L CNN
F 1 "CONN_1" H 11700 10255 30 0001 C CNN
1 11700 10200
0 -1 -1 0
$EndComp
$Comp
L CONN_1 P10
U 1 1 4FB81E53
P 11800 10200
F 0 "P10" H 11880 10200 40 0000 L CNN
F 1 "CONN_1" H 11800 10255 30 0001 C CNN
1 11800 10200
0 -1 -1 0
$EndComp
$Comp
L CONN_1 P11
U 1 1 4FB81E51
P 11900 10200
F 0 "P11" H 11980 10200 40 0000 L CNN
F 1 "CONN_1" H 11900 10255 30 0001 C CNN
1 11900 10200
0 -1 -1 0
$EndComp
$Comp
L CONN_1 P12
U 1 1 4FB81E45
P 12000 10200
F 0 "P12" H 12080 10200 40 0000 L CNN
F 1 "CONN_1" H 12000 10255 30 0001 C CNN
1 12000 10200
0 -1 -1 0
$EndComp
Text Notes 14800 8100 0 40 ~ 0
balun here will not be needed when a\nboard is made with a direct connection\nto the MAX2837
Wire Wire Line