fixed REF_IN comment
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@ -1,4 +1,4 @@
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EESchema-LIBRARY Version 2.3 Date: Sat May 19 15:59:16 2012
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EESchema-LIBRARY Version 2.3 Date: Sat May 19 16:05:01 2012
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#encoding utf-8
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#
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# BALUN
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@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Sat May 19 15:59:16 2012
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EESchema Schematic File Version 2 date Sat May 19 16:05:01 2012
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -1199,7 +1199,7 @@ F 1 "1n8" V 7850 4300 40 0000 C CNN
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1 0 0 -1
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$EndComp
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Text Notes 4550 9550 0 40 ~ 0
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Clock input should be 1.1 to 3.3 V\npeak-to-peak. It is divided down to\n0.5 to 1.5 V (REF_IN).
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Expected clock input is 1.8 to 3.3 V\npeak-to-peak at 25 to 52 MHz. It is\ndivided down to 0.5 to 1.5 V (REF_IN).
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$Comp
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L C C77
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U 1 1 4FB3CC76
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