From 64656d1e92e68861627ebd84bbe00676872047b6 Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Mon, 2 Jul 2012 11:30:44 -0700 Subject: [PATCH] SGPIO passthrough CPLD project, for TitanMKD's testing. --- .../jellybean/sgpio_if_passthrough/README.md | 33 + .../jellybean/sgpio_if_passthrough/program | 10 + .../sgpio_if_passthrough.svf | 2079 +++++++++++++++++ .../sgpio_if_passthrough.xise | 242 ++ .../jellybean/sgpio_if_passthrough/top.ucf | 89 + .../jellybean/sgpio_if_passthrough/top.vhd | 60 + 6 files changed, 2513 insertions(+) create mode 100644 hardware/jellybean/sgpio_if_passthrough/README.md create mode 100755 hardware/jellybean/sgpio_if_passthrough/program create mode 100755 hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.svf create mode 100755 hardware/jellybean/sgpio_if_passthrough/sgpio_if_passthrough.xise create mode 100755 hardware/jellybean/sgpio_if_passthrough/top.ucf create mode 100755 hardware/jellybean/sgpio_if_passthrough/top.vhd diff --git a/hardware/jellybean/sgpio_if_passthrough/README.md b/hardware/jellybean/sgpio_if_passthrough/README.md new file mode 100644 index 00000000..2fc7a383 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/README.md @@ -0,0 +1,33 @@ + +CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either +as all inputs or all outputs. + +Requirements +============ + +To build this VHDL project and produce an SVF file for flashing the CPLD: + +* Xilinx WebPACK 13.4 for Windows or Linux. + +* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com, + in the "Device Models" Support Resources section of the CoolRunner-II + Product Support & Documentation page. Only one file from the BSDL package is + required, and the "program" script below expects it to be at the relative + path "bsdl/xc2c/xc2c64.bsd". + +To program the SVF file into the CPLD: + +* Dangerous Prototypes Bus Blaster v2: + * Configured with JTAGKey buffers. + * Connected to CPLD JTAG signals on Jellybean. + +* urJTAG built with libftdi support. + +To Program +========== + +./program + +...which connects to the Bus Blaster interface 0, sets the BSDL directory, +detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf +file to the CPLD. diff --git a/hardware/jellybean/sgpio_if_passthrough/program b/hardware/jellybean/sgpio_if_passthrough/program new file mode 100755 index 00000000..0aba6b0e --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/program @@ -0,0 +1,10 @@ +#!/bin/sh + +echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2 + +jtag < + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hardware/jellybean/sgpio_if_passthrough/top.ucf b/hardware/jellybean/sgpio_if_passthrough/top.ucf new file mode 100755 index 00000000..cd6a2e70 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/top.ucf @@ -0,0 +1,89 @@ +# +# Copyright 2012 Jared Boone +# +# This file is part of HackRF. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. + +NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18; +NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18; +#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18; + +NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK; +TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns; + +NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18; +NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18; + +NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18; +NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18; + +NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18; +NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18; + +NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33; +NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33; + +NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33; +NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33; diff --git a/hardware/jellybean/sgpio_if_passthrough/top.vhd b/hardware/jellybean/sgpio_if_passthrough/top.vhd new file mode 100755 index 00000000..55be76b6 --- /dev/null +++ b/hardware/jellybean/sgpio_if_passthrough/top.vhd @@ -0,0 +1,60 @@ +-- +-- Copyright 2012 Jared Boone +-- +-- This file is part of HackRF. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; see the file COPYING. If not, write to +-- the Free Software Foundation, Inc., 51 Franklin Street, +-- Boston, MA 02110-1301, USA. + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity top is + Port( + SGPIO : inout std_logic_vector(15 downto 0); + + DA : in std_logic_vector(7 downto 0); + DD : out std_logic_vector(9 downto 0); + + CODEC_CLK : in std_logic; + CODEC_X2_CLK : in std_logic; + + B1AUX : in std_logic_vector(16 downto 9); + B2AUX : inout std_logic_vector(16 downto 1) + ); + +end top; + +architecture Behavioral of top is + type transfer_direction is (to_sgpio, from_sgpio); + signal transfer_direction_i : transfer_direction; + +begin + + transfer_direction_i <= to_sgpio when B1AUX(9) = '0' + else from_sgpio; + + DD <= (DD'high => '1', others => '0'); + + B2AUX <= SGPIO when transfer_direction_i = from_sgpio + else (others => 'Z'); + + SGPIO <= B2AUX when transfer_direction_i = to_sgpio + else (others => 'Z'); + +end Behavioral;