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h1r9: use MAX2839

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This commit is contained in:
Michael Ossmann
2022-09-17 14:43:48 -04:00
committed by Mike Walters
parent 14183a96ea
commit 3738270e4f
6 changed files with 91 additions and 44 deletions
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49
firmware/common/hackrf_core.c
View File

@ -28,6 +28,8 @@
#include "spi_ssp.h"
#include "max2837.h"
#include "max2837_target.h"
#include "max2839.h"
#include "max2839_target.h"
#include "max5864.h"
#include "max5864_target.h"
#include "w25q80bv.h"
@ -189,6 +191,20 @@ const ssp_config_t ssp_config_max2837 = {
.gpio_select = &gpio_max2837_select,
};
const ssp_config_t ssp_config_max2839 = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.data_bits = SSP_DATA_16BITS,
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
.gpio_select = &gpio_max2837_select,
};
const ssp_config_t ssp_config_max5864 = {
/* FIXME speed up once everything is working reliably */
/*
@ -205,7 +221,7 @@ const ssp_config_t ssp_config_max5864 = {
spi_bus_t spi_bus_ssp1 = {
.obj = (void*) SSP1_BASE,
.config = &ssp_config_max2837,
.config = &ssp_config_max5864,
.start = spi_ssp_start,
.stop = spi_ssp_stop,
.transfer = spi_ssp_transfer,
@ -221,6 +237,14 @@ max2837_driver_t max2837 = {
.set_mode = max2837_target_set_mode,
};
max2839_driver_t max2839 = {
.bus = &spi_bus_ssp1,
.gpio_enable = &gpio_max2837_enable,
.gpio_rxtx = &gpio_max2837_rx_enable,
.target_init = max2839_target_init,
.set_mode = max2839_target_set_mode,
};
max5864_driver_t max5864 = {
.bus = &spi_bus_ssp1,
.target_init = max5864_target_init,
@ -534,7 +558,12 @@ bool sample_rate_set(const uint32_t sample_rate_hz)
bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz)
{
uint32_t bandwidth_hz_real = max2837_set_lpf_bandwidth(&max2837, bandwidth_hz);
uint32_t bandwidth_hz_real;
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
bandwidth_hz_real = max2839_set_lpf_bandwidth(&max2839, bandwidth_hz);
} else {
bandwidth_hz_real = max2837_set_lpf_bandwidth(&max2837, bandwidth_hz);
}
if (bandwidth_hz_real) {
hackrf_ui()->set_filter_bw(bandwidth_hz_real);
@ -636,7 +665,7 @@ void cpu_clock_init(void)
/*
* Clocks on HackRF One r9:
* CLK0 -> MAX5864/CPLD/SGPIO (sample clocks)
* CLK1 -> RFFC5072/MAX2837
* CLK1 -> RFFC5072/MAX2839
* CLK2 -> External Clock Output/LPC43xx (power down at boot)
*
* Clocks on other platforms:
@ -651,7 +680,7 @@ void cpu_clock_init(void)
*/
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
/* MS0/CLK0 is the reference for both RFFC5071 and MAX2837. */
/* MS0/CLK0 is the reference for both RFFC5071 and MAX2839. */
si5351c_configure_multisynth(
&clock_gen,
0,
@ -868,6 +897,11 @@ void ssp1_set_mode_max2837(void)
spi_bus_start(max2837.bus, &ssp_config_max2837);
}
void ssp1_set_mode_max2839(void)
{
spi_bus_start(max2839.bus, &ssp_config_max2839);
}
void ssp1_set_mode_max5864(void)
{
spi_bus_start(max5864.bus, &ssp_config_max5864);
@ -960,8 +994,11 @@ void pin_setup(void)
/* enable input on SCL and SDA pins */
SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
//FIXME
//spi_bus_start(&spi_bus_ssp1, &ssp_config_max2837);
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
spi_bus_start(&spi_bus_ssp1, &ssp_config_max2839);
} else {
spi_bus_start(&spi_bus_ssp1, &ssp_config_max2837);
}
mixer_bus_setup(&mixer);

4
firmware/common/hackrf_core.h
View File

@ -35,6 +35,7 @@ extern "C" {
#include "spi_ssp.h"
#include "max2837.h"
#include "max2839.h"
#include "max5864.h"
#include "mixer.h"
#include "w25q80bv.h"
@ -267,9 +268,11 @@ void delay_us_at_mhz(uint32_t us, uint32_t mhz);
extern si5351c_driver_t clock_gen;
extern const ssp_config_t ssp_config_w25q80bv;
extern const ssp_config_t ssp_config_max2837;
extern const ssp_config_t ssp_config_max2839;
extern const ssp_config_t ssp_config_max5864;
extern max2837_driver_t max2837;
extern max2839_driver_t max2839; //FIXME xcvr hal
extern max5864_driver_t max5864;
extern mixer_driver_t mixer;
extern w25q80bv_driver_t spi_flash;
@ -280,6 +283,7 @@ extern i2c_bus_t i2c0;
void cpu_clock_init(void);
void ssp1_set_mode_max2837(void);
void ssp1_set_mode_max2839(void);
void ssp1_set_mode_max5864(void);
void pin_setup(void);

3
firmware/common/max2839.h
View File

@ -49,8 +49,7 @@ typedef struct max2839_driver_t max2839_driver_t;
struct max2839_driver_t {
spi_bus_t* const bus;
gpio_t gpio_enable;
gpio_t gpio_rx_enable;
gpio_t gpio_tx_enable;
gpio_t gpio_rxtx;
void (*target_init)(max2839_driver_t* const drv);
void (*set_mode)(max2839_driver_t* const drv, const max2839_mode_t new_mode);
max2839_mode_t mode;

68
firmware/common/max2839_regs.def
View File

@ -28,13 +28,13 @@ static inline void set_##n(max2839_driver_t* const _d, uint16_t v) { \
}
/* REG 0 */
__MREG__(MAX2839_RESERVED_1, 0,9,10)
__MREG__(MAX2839_RESERVED_0_9,0,9,10)
/* REG 1 */
__MREG__(MAX2839_LNAband,1,1,2)
#define MAX2839_LNAband_2_4 0 // 2.3-2.5 GHz
#define MAX2839_LNAband_2_6 1 // 2.5-2.7 GHz
__MREG__(MAX2839_RESERVED_2,1,2,1)
__MREG__(MAX2839_RESERVED_1_2,1,2,1)
__MREG__(MAX2839_MIMO_SELECT,1,3,1)
__MREG__(MAX2839_iqerr_trim,1,9,6)
// TODO: D9:D4 but shows only 5 bits for values?
@ -44,17 +44,17 @@ __MREG__(MAX2839_iqerr_trim,1,9,6)
/* REG 2 */
__MREG__(MAX2839_LNAgain_SPI,2,0,1)
__MREG__(MAX2839_RESERVED_3,2,1,1)
__MREG__(MAX2839_RESERVED_2_1,2,1,1)
__MREG__(MAX2839_RX_IQ_SPI,2,2,1)
__MREG__(MAX2839_RESERVED_4,2,9,7)
__MREG__(MAX2839_RESERVED_2_9,2,9,7)
/* REG 3 */
__MREG__(MAX2839_RESERVED_5,3,9,10)
__MREG__(MAX2839_RESERVED_3_9,3,9,10)
/* REG 4 */
__MREG__(MAX2839_RESERVED_6,4,1,2)
__MREG__(MAX2839_RESERVED_4_1,4,1,2)
__MREG__(MAX2839_LPF_CUTOFF,4,3,2)
__MREG__(MAX2839_RESERVED_7,4,5,2)
__MREG__(MAX2839_RESERVED_4_5,4,5,2)
__MREG__(MAX2839_FT,4,9,4)
#define MAX2839_FT_1_75M 0
#define MAX2839_FT_2_5M 1
@ -92,36 +92,36 @@ __MREG__(MAX2839_Rx2_VGAgain,6,7,6)
__MREG__(MAX2839_RX_VGAoutput,6,9,2)
/* REG 7 */
__MREG__(MAX2839_RESERVED_7,7,0,1)
__MREG__(MAX2839_RESERVED_7_0,7,0,1)
__MREG__(MAX2839_RSSIselect,7,1,1)
__MREG__(MAX2839_RSSImode,7,2,1)
__MREG__(MAX2839_RESERVED_8,7,6,4)
__MREG__(MAX2839_RESERVED_7_6,7,6,4)
__MREG__(MAX2839_RXBBI_RXBBQ,7,7,1)
__MREG__(MAX2839_RESERVED_9,7,8,1)
__MREG__(MAX2839_RESERVED_7_8,7,8,1)
__MREG__(MAX2839_RSSIinput,7,9,1)
/* REG 8 */
__MREG__(MAX2839_RESERVED_8,8,0,1)
__MREG__(MAX2839_RESERVED_8_0,8,0,1)
__MREG__(MAX2839_VGAgain_SPI,8,1,1)
__MREG__(MAX2839_LPFmode,8,2,1)
__MREG__(MAX2839_RESERVED_9,8,9,7)
__MREG__(MAX2839_RESERVED_8_9,8,9,7)
/* REG 9 */
__MREG__(MAX2839_Temperature_ADC,9,0,1)
__MREG__(MAX2839_Temperature_Clk_En,9,1,1)
__MREG__(MAX2839_RESERVED_10,9,2,1)
__MREG__(MAX2839_RESERVED_9_2,9,2,1)
__MREG__(MAX2839_DOUT_Drive_Sel,9,3,1)
__MREG__(MAX2839_DOUT_3state_Ctrl,9,4,1)
__MREG__(MAX2839_DOUT_Pin_Sel,9,7,3)
__MREG__(MAX2839_RESERVED_11,9,9,2)
__MREG__(MAX2839_RESERVED_9_9,9,9,2)
/* REG 10 */
__MREG__(MAX2839_TX_AM_gain,10,1,2)
__MREG__(MAX2839_TX_AM_bandwidth,10,4,3)
__MREG__(MAX2839_RESERVED_12,10,9,5)
__MREG__(MAX2839_RESERVED_10_9,10,9,5)
/* REG 11 */
__MREG__(MAX2839_RESERVED_13,11,9,10)
__MREG__(MAX2839_RESERVED_11_9,11,9,10)
/* REG 12 */
__MREG__(MAX2839_RXVGA_10M_RXEN_duration,12,1,2)
@ -146,18 +146,18 @@ __MREG__(MAX2839_PA_DRV_DAC,14,9,1)
/* REG 15 */
__MREG__(MAX2839_RXVGA_HPFSM_Clk_Divider,15,0,1)
__MREG__(MAX2839_RESERVED_14,15,5,5)
__MREG__(MAX2839_RESERVED_15_5,15,5,5)
__MREG__(MAX2839_RXHP_sequence_bypass,15,6,1)
__MREG__(MAX2839_RESERVED_15,15,8,2)
__MREG__(MAX2839_RESERVED_15_8,15,8,2)
__MREG__(MAX2839_RXHP_highpass_corner,15,9,1)
/* REG 16 */
__MREG__(MAX2839_chip_enable,16,0,1)
__MREG__(MAX2839_RXTX_calibration_enable,16,1,1)
__MREG__(MAX2839_RESERVED_16,16,5,4)
__MREG__(MAX2839_RESERVED_16_5,16,5,4)
__MREG__(MAX2839_PA_bias_DAC_SPI_enable,16,6,1)
__MREG__(MAX2839_PA_bias_DAC_TX_mode_enable,16,7,1)
__MREG__(MAX2839_RESERVED_17,16,9,2)
__MREG__(MAX2839_RESERVED_16_9,16,9,2)
/* REG 17 */
__MREG__(MAX2839_SYN_FRAC_LO,17,9,10)
@ -174,14 +174,14 @@ __MREG__(MAX2839_LOGEN_BSW,19,9,2)
#define MAX2839_LOGEN_BSW_2_6 3 // 2600 - <2700 MHz
/* REG 20 */
__MREG__(MAX2839_RESERVED_18,20,0,1)
__MREG__(MAX2839_RESERVED_20_0,20,0,1)
__MREG__(MAX2839_Reference_Divider_Ratio,20,2,2)
__MREG__(MAX2839_RESERVED_19,20,4,2)
__MREG__(MAX2839_RESERVED_20_4,20,4,2)
__MREG__(MAX2839_CLKOUT_Buffer_Drive,20,5,1)
__MREG__(MAX2839_RESERVED_20,20,9,4)
__MREG__(MAX2839_RESERVED_20_9,20,9,4)
/* REG 21 */
__MREG__(MAX2839_RESERVED_21,21,9,10)
__MREG__(MAX2839_RESERVED_21_9,21,9,10)
/* REG 22 */
__MREG__(MAX2839_VAS_Operating_Mode_Select,22,0,1)
@ -189,26 +189,26 @@ __MREG__(MAX2839_VAS_Relock_Mode_Select,22,1,1)
__MREG__(MAX2839_VAS_Clk_Divide_Ratio,22,4,3)
__MREG__(MAX2839_VAS_Delay_Counter_Ratio,22,6,2)
__MREG__(MAX2839_VAS_Addr17_Trigger_Enable,22,7,1)
__MREG__(MAX2839_RESERVED_22,22,9,2)
__MREG__(MAX2839_RESERVED_22_9,22,9,2)
/* REG 23 */
__MREG__(MAX2839_VAS_Subband_SPI_Overwrite,23,4,5)
__MREG__(MAX2839_Crystal_Oscillator_Bias_Select,23,6,2)
__MREG__(MAX2839_RESERVED_23,23,9,3)
__MREG__(MAX2839_RESERVED_23_9,23,9,3)
/* REG 24 */
__MREG__(MAX2839_Crystal_Oscillator_Freq_Tuning,24,6,7)
__MREG__(MAX2839_RESERVED_24,24,7,1)
__MREG__(MAX2839_RESERVED_24_7,24,7,1)
__MREG__(MAX2839_CLKOUT_Divide_Ratio,24,8,1)
__MREG__(MAX2839_Crystal_Oscillator_Core_Enable,24,9,1)
/* REG 25 */
__MREG__(MAX2839_RESERVED_25,25,9,10)
__MREG__(MAX2839_RESERVED_25_9,25,9,10)
/* REG 26 */
__MREG__(MAX2839_RESERVED_26,26,2,3)
__MREG__(MAX2839_RESERVED_26_2,26,2,3)
__MREG__(MAX2839_LOGEN_RXTX_Gm_Enable,26,3,1)
__MREG__(MAX2839_RESERVED_27,26,5,2)
__MREG__(MAX2839_RESERVED_26_5,26,5,2)
__MREG__(MAX2839_VAS_Test_Signal_Select,26,9,4)
/* REG 27 */
@ -216,7 +216,7 @@ __MREG__(MAX2839_TX_LO_IQ_Phase_SPI_Adjust_Addr27,27,5,6)
__MREG__(MAX2839_TX_LO_IQ_Phase_SPI_Adjust_Enable,27,6,1)
__MREG__(MAX2839_TX_VGA_Gain_SPI_Ctrl_Enable,27,7,1)
__MREG__(MAX2839_TX_DC_Offset_SPI_Adjust_Enable,27,8,1)
__MREG__(MAX2839_RESERVED_28,27,9,1)
__MREG__(MAX2839_RESERVED_27_9,27,9,1)
/* REG 28 */
__MREG__(MAX2839_PADAC_Output_Current_Ctrl,28,5,6)
@ -224,17 +224,17 @@ __MREG__(MAX2839_PADAC_TurnOn_Delay_Ctrl,28,9,4)
/* REG 29 */
__MREG__(MAX2839_TX_VGA_GAIN,29,5,6)
__MREG__(MAX2839_RESERVED_29,29,9,4)
__MREG__(MAX2839_RESERVED_29_9,29,9,4)
/* REG 30 */
__MREG__(MAX2839_TX_DC_Offset_Correction_Addr27,30,5,6)
__MREG__(MAX2839_RESERVED_30,30,7,2)
__MREG__(MAX2839_RESERVED_30_7,30,7,2)
__MREG__(MAX2839_PA_DAC_IV_Output_Select,30,8,1)
__MREG__(MAX2839_PA_DAC_Voltage_Mode_Output_Select,30,9,1)
/* REG 31 */
__MREG__(MAX2839_TX_DC_Offset_Correction_QChannel,31,5,6)
__MREG__(MAX2839_RESERVED_31,31,8,3)
__MREG__(MAX2839_RESERVED_31_8,31,8,3)
__MREG__(MAX2839_PA_DAC_Clk_Divide_Ratio,31,9,1)
#endif // __MAX2839_REGS_DEF

9
firmware/common/rf_path.c
View File

@ -371,8 +371,13 @@ void rf_path_init(rf_path_t* const rf_path)
max5864_shutdown(&max5864);
ssp1_set_mode_max2837();
max2837_setup(&max2837);
max2837_start(&max2837);
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
max2839_setup(&max2839);
max2839_start(&max2839);
} else {
max2837_setup(&max2837);
max2837_start(&max2837);
}
// On HackRF One, the mixer is now set up earlier in boot.
#ifndef HACKRF_ONE

2
firmware/hackrf-common.cmake
View File

@ -172,6 +172,8 @@ macro(DeclareTargets)
${PATH_HACKRF_FIRMWARE_COMMON}/si5351c.c
${PATH_HACKRF_FIRMWARE_COMMON}/max2837.c
${PATH_HACKRF_FIRMWARE_COMMON}/max2837_target.c
${PATH_HACKRF_FIRMWARE_COMMON}/max2839.c
${PATH_HACKRF_FIRMWARE_COMMON}/max2839_target.c
${PATH_HACKRF_FIRMWARE_COMMON}/max5864.c
${PATH_HACKRF_FIRMWARE_COMMON}/max5864_target.c
${PATH_HACKRF_FIRMWARE_COMMON}/mixer.c