h1r9: implement additional MAX2839 functions, change some mreg definition names, fix RF gain control math
This commit is contained in:
grvvy
@ -56,11 +56,6 @@ static const uint16_t max2839_regs_default[MAX2839_NUM_REGS] = {
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0x155, /* 18 */
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0x153, /* 19 */
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0x249, /* 20 */
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/*
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* Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
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* does not work. Page 1 of the SPI doc says not to set it (0x02c), but
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* page 21 says it should be set by default (0x02d).
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*/
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0x02d, /* 21 */
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0x1a9, /* 22 */
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0x24f, /* 23 */
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@ -83,7 +78,7 @@ static void max2839_init(max2839_driver_t* const drv)
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drv->regs_dirty = 0xffffffff;
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/* Write default register values to chip. */
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max2837_regs_commit(drv);
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max2839_regs_commit(drv);
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}
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/*
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@ -152,35 +147,85 @@ max2839_mode_t max2839_mode(max2839_driver_t* const drv)
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void max2839_start(max2839_driver_t* const drv)
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{
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set_MAX2839_EN_SPI(drv, 1);
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set_MAX2839_chip_enable(drv, 1);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_STANDBY);
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}
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void max2839_tx(max2839_driver_t* const drv)
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{
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// TODO
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set_MAX2839_LPFblock_MODE(drv, MAX2839_ModeCtrl_TxLPF);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_TX);
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}
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void max2839_rx(max2839_driver_t* const drv)
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{
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// TODO
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set_MAX2839_LPFblock_MODE(drv, MAX2839_ModeCtrl_RxLPF);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_RX);
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}
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void max2839_stop(max2839_driver_t* const drv)
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{
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// TODO
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set_MAX2839_chip_enable(drv, 0);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_SHUTDOWN);
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}
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void max2839_set_frequency(max2839_driver_t* const drv, uint32_t freq)
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{
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// TODO
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uint8_t band;
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uint8_t lna_band;
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uint32_t div_frac;
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uint32_t div_int;
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uint32_t div_rem;
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uint32_t div_cmp;
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int i;
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/* Select band. Allow tuning outside specified bands. */
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if (freq < 2400000000U) {
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band = MAX2839_LOGEN_BSW_2_3;
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lna_band = MAX2839_LNAband_2_4;
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} else if (freq < 2500000000U) {
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band = MAX2839_LOGEN_BSW_2_4;
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lna_band = MAX2839_LNAband_2_4;
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} else if (freq < 2600000000U) {
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band = MAX2839_LOGEN_BSW_2_5;
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lna_band = MAX2839_LNAband_2_6;
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} else {
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band = MAX2839_LOGEN_BSW_2_6;
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lna_band = MAX2839_LNAband_2_6;
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}
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/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
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div_int = freq / 30000000;
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div_rem = freq % 30000000;
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div_frac = 0;
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div_cmp = 30000000;
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for (i = 0; i < 20; i++) {
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div_frac <<= 1;
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div_cmp >>= 1;
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if (div_rem > div_cmp) {
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div_frac |= 0x1;
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div_rem -= div_cmp;
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}
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}
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/* Band settings */
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set_MAX2839_LOGEN_BSW(drv, band);
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set_MAX2839_LNAband(drv, lna_band);
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/* Write order matters here, so commit INT and FRAC_HI before
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* committing FRAC_LO, which is the trigger for VCO
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* auto-select. TODO - it's cleaner this way, but it would be
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* faster to explicitly commit the registers explicitly so the
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* dirty bits aren't scanned twice. */
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set_MAX2839_SYN_INT(drv, div_int);
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set_MAX2839_SYN_FRAC_HI(drv, (div_frac >> 10) & 0x3ff);
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max2839_regs_commit(drv);
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set_MAX2839_SYN_FRAC_LO(drv, div_frac & 0x3ff);
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max2839_regs_commit(drv);
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}
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typedef struct {
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@ -229,25 +274,27 @@ uint32_t max2839_set_lpf_bandwidth(max2839_driver_t* const drv, const uint32_t b
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bool max2839_set_lna_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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uint16_t val;
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// TODO: validate steps here
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switch(gain_db){
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case 40:
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val = MAX2839_LNAgain_MAX;
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val = MAX2839_LNA1gain_MAX;
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break;
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case 32:
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val = MAX2839_LNAgain_M8;
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val = MAX2839_LNA1gain_M8;
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break;
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case 24:
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val = MAX2839_LNAgain_M16;
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val = MAX2839_LNA1gain_M16;
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break;
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case 8:
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val = MAX2839_LNAgain_M32;
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val = MAX2839_LNA1gain_M32;
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break;
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case 0:
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val = MAX2839_LNA1gain_M32;
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break;
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default:
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return false;
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}
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set_MAX2839_LNAgain(drv, val);
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max2839_reg_commit(drv, 1);
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set_MAX2839_LNA1gain(drv, val);
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max2839_reg_commit(drv, 5);
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return true;
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}
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@ -256,21 +303,16 @@ bool max2839_set_vga_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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return false;
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}
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set_MAX2839_VGA(drv, 31-(gain_db >> 1) );
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set_MAX2839_Rx1_VGAgain(drv, (63-gain_db));
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max2839_reg_commit(drv, 5);
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return true;
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}
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bool max2839_set_txvga_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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uint16_t val=0;
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if(gain_db <16){
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val = 31-gain_db;
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val |= (1 << 5); // bit6: 16db
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} else{
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val = 31-(gain_db-16);
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}
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val = 63-gain_db;
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set_MAX2839_TXVGA_GAIN(drv, val);
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set_MAX2839_TX_VGA_GAIN(drv, val);
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max2839_reg_commit(drv, 29);
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return true;
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}
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@ -31,7 +31,9 @@ static inline void set_##n(max2839_driver_t* const _d, uint16_t v) { \
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__MREG__(MAX2839_RESERVED_1, 0,9,10)
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/* REG 1 */
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__MREG__(MAX2839_LNAtune,1,1,2)
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__MREG__(MAX2839_LNAband,1,1,2)
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#define MAX2839_LNAband_2_4 0 // 2.3-2.5 GHz
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#define MAX2839_LNAband_2_6 1 // 2.5-2.7 GHz
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__MREG__(MAX2839_RESERVED_2,1,2,1)
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__MREG__(MAX2839_MIMO_SELECT,1,3,1)
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__MREG__(MAX2839_iqerr_trim,1,9,6)
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@ -53,7 +55,7 @@ __MREG__(MAX2839_RESERVED_5,3,9,10)
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__MREG__(MAX2839_RESERVED_6,4,1,2)
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__MREG__(MAX2839_LPF_CUTOFF,4,3,2)
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__MREG__(MAX2839_RESERVED_7,4,5,2)
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__MREG__(MAX2839_LPF_RF_BAND,4,9,4)
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__MREG__(MAX2839_FT,4,9,4)
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#define MAX2839_FT_1_75M 0
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#define MAX2839_FT_2_5M 1
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#define MAX2839_FT_3_5M 2
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@ -72,13 +74,17 @@ __MREG__(MAX2839_LPF_RF_BAND,4,9,4)
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#define MAX2839_FT_28M 15
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/* REG 5 */
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__MREG__(MAX2839_LNA1gain_SPI,5,1,2)
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#define MAX2839_LNAgain_MAX 0b000 // Pad in 8dB steps, bits reversed
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#define MAX2839_LNAgain_M8 0b001
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#define MAX2839_LNAgain_M16 0b010
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#define MAX2839_LNAgain_M32 0b011
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__MREG__(MAX2839_LNA1gain,5,1,2)
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#define MAX2839_LNA1gain_MAX 0b000 // Pad in 8dB steps, bits reversed
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#define MAX2839_LNA1gain_M8 0b001
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#define MAX2839_LNA1gain_M16 0b010
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#define MAX2839_LNA1gain_M32 0b011
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__MREG__(MAX2839_Rx1_VGAgain,5,7,6)
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__MREG__(MAX2839_LPFblock_MODE,5,9,2)
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#define MAX2839_ModeCtrl_RxCalibration 0
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#define MAX2839_ModeCtrl_RxLPF 1
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#define MAX2839_ModeCtrl_TxLPF 2
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#define MAX2839_ModeCtrl_LPFTrim 3
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/* REG 6 */
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__MREG__(MAX2839_LNA2gain_SPI,6,1,2)
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@ -146,7 +152,7 @@ __MREG__(MAX2839_RESERVED_15,15,8,2)
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__MREG__(MAX2839_RXHP_highpass_corner,15,9,1)
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/* REG 16 */
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__MREG__(MAX2839_chip_disable,16,0,1)
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__MREG__(MAX2839_chip_enable,16,0,1)
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__MREG__(MAX2839_RXTX_calibration_enable,16,1,1)
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__MREG__(MAX2839_RESERVED_16,16,5,4)
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__MREG__(MAX2839_PA_bias_DAC_SPI_enable,16,6,1)
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@ -154,14 +160,18 @@ __MREG__(MAX2839_PA_bias_DAC_TX_mode_enable,16,7,1)
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__MREG__(MAX2839_RESERVED_17,16,9,2)
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/* REG 17 */
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__MREG__(MAX2839_SYNTH_20bit_FDR_UH,17,9,10)
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__MREG__(MAX2839_SYN_FRAC_LO,17,9,10)
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/* REG 18 */
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__MREG__(MAX2839_SYNTH_20bit_FDR_LH,18,9,10)
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__MREG__(MAX2839_SYN_FRAC_HI,18,9,10)
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/* REG 19 */
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__MREG__(MAX2839_SYNTH_8bit_IDR,19,7,8)
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__MREG__(MAX2839_LO_Gen_Band_Switch,19,9,2)
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__MREG__(MAX2839_SYN_INT,19,7,8)
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__MREG__(MAX2839_LOGEN_BSW,19,9,2)
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#define MAX2839_LOGEN_BSW_2_3 0 // 2300 - <2400 MHz
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#define MAX2839_LOGEN_BSW_2_4 1 // 2400 - <2500 MHz
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#define MAX2839_LOGEN_BSW_2_5 2 // 2500 - <2600 MHz
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#define MAX2839_LOGEN_BSW_2_6 3 // 2600 - <2700 MHz
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/* REG 20 */
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__MREG__(MAX2839_RESERVED_18,20,0,1)
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@ -213,7 +223,7 @@ __MREG__(MAX2839_PADAC_Output_Current_Ctrl,28,5,6)
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__MREG__(MAX2839_PADAC_TurnOn_Delay_Ctrl,28,9,4)
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/* REG 29 */
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__MREG__(MAX2839_TX_VGA_SPI_Gain_Ctrl_Addr27,29,5,6)
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__MREG__(MAX2839_TX_VGA_GAIN,29,5,6)
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__MREG__(MAX2839_RESERVED_29,29,9,4)
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/* REG 30 */
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