h1r9: add preliminary MAX2839 driver and accompanying header file; add some convenience macros to regs_def
This commit is contained in:
grvvy
276
firmware/common/max2839.c
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276
firmware/common/max2839.c
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@ -0,0 +1,276 @@
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/*
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* Copyright 2012 Will Code? (TODO: Proper attribution)
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* Copyright 2014 Jared Boone <jared@sharebrained.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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/*
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* 'gcc -DTEST -DDEBUG -O2 -o test max2839.c' prints out what test
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* program would do if it had a real spi library
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*
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* 'gcc -DTEST -DBUS_PIRATE -O2 -o test max2839.c' prints out bus
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* pirate commands to do the same thing.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "max2839.h"
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#include "max2839_regs.def" // private register def macros
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/* Default register values. */
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static const uint16_t max2839_regs_default[MAX2839_NUM_REGS] = {
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0x000, /* 0 */
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0x00C, /* 1 */
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0x080, /* 2 */
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0x1b9, /* 3 */
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0x3e6, /* 4 */
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0x100, /* 5 */
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0x000, /* 6 */
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0x208, /* 7 */
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0x220, /* 8 */
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0x018, /* 9 */
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0x00c, /* 10 */
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0x004, /* 11 */
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0x24f, /* 12 */
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0x150, /* 13 */
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0x3c5, /* 14 */
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0x201, /* 15 */
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0x01c, /* 16 */
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0x155, /* 17 */
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0x155, /* 18 */
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0x153, /* 19 */
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0x249, /* 20 */
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/*
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* Charge Pump Common Mode Enable bit (0) of register 21 must be set or TX
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* does not work. Page 1 of the SPI doc says not to set it (0x02c), but
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* page 21 says it should be set by default (0x02d).
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*/
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0x02d, /* 21 */
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0x1a9, /* 22 */
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0x24f, /* 23 */
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0x180, /* 24 */
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0x000, /* 25 */
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0x3c0, /* 26 */
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0x200, /* 27 */
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0x0c0, /* 28 */
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0x03f, /* 29 */
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0x380, /* 30 */
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0x340}; /* 31 */
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/* Set up all registers according to defaults specified in docs. */
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static void max2839_init(max2839_driver_t* const drv)
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{
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drv->target_init(drv);
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max2839_set_mode(drv, MAX2839_MODE_SHUTDOWN);
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memcpy(drv->regs, max2839_regs_default, sizeof(drv->regs));
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drv->regs_dirty = 0xffffffff;
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/* Write default register values to chip. */
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max2837_regs_commit(drv);
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}
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/*
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* Set up pins for GPIO and SPI control, configure SSP peripheral for SPI, and
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* set our own default register configuration.
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*/
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void max2839_setup(max2839_driver_t* const drv)
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{
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max2839_init(drv);
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// TODO
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max2839_regs_commit(drv);
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}
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static uint16_t max2839_read(max2839_driver_t* const drv, uint8_t r)
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{
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uint16_t value = (1 << 15) | (r << 10);
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spi_bus_transfer(drv->bus, &value, 1);
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return value & 0x3ff;
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}
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static void max2839_write(max2839_driver_t* const drv, uint8_t r, uint16_t v)
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{
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uint16_t value = (r << 10) | (v & 0x3ff);
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spi_bus_transfer(drv->bus, &value, 1);
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}
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uint16_t max2839_reg_read(max2839_driver_t* const drv, uint8_t r)
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{
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if ((drv->regs_dirty >> r) & 0x1) {
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drv->regs[r] = max2839_read(drv, r);
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};
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return drv->regs[r];
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}
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void max2839_reg_write(max2839_driver_t* const drv, uint8_t r, uint16_t v)
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{
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drv->regs[r] = v;
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max2839_write(drv, r, v);
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MAX2839_REG_SET_CLEAN(drv, r);
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}
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static inline void max2839_reg_commit(max2839_driver_t* const drv, uint8_t r)
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{
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max2839_reg_write(drv, r, drv->regs[r]);
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}
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void max2839_regs_commit(max2839_driver_t* const drv)
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{
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int r;
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for (r = 0; r < MAX2839_NUM_REGS; r++) {
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if ((drv->regs_dirty >> r) & 0x1) {
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max2839_reg_commit(drv, r);
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}
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}
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}
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void max2839_set_mode(max2839_driver_t* const drv, const max2839_mode_t new_mode)
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{
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drv->set_mode(drv, new_mode);
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}
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max2839_mode_t max2839_mode(max2839_driver_t* const drv)
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{
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return drv->mode;
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}
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void max2839_start(max2839_driver_t* const drv)
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{
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set_MAX2839_EN_SPI(drv, 1);
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_STANDBY);
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}
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void max2839_tx(max2839_driver_t* const drv)
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{
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// TODO
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_TX);
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}
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void max2839_rx(max2839_driver_t* const drv)
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{
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// TODO
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_RX);
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}
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void max2839_stop(max2839_driver_t* const drv)
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{
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// TODO
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max2839_regs_commit(drv);
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max2839_set_mode(drv, MAX2839_MODE_SHUTDOWN);
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}
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void max2839_set_frequency(max2839_driver_t* const drv, uint32_t freq)
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{
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// TODO
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}
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typedef struct {
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uint32_t bandwidth_hz;
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uint32_t ft;
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} max2839_ft_t;
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// clang-format off
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static const max2839_ft_t max2839_ft[] = {
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{ 1750000, MAX2839_FT_1_75M },
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{ 2500000, MAX2839_FT_2_5M },
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{ 3500000, MAX2839_FT_3_5M },
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{ 5000000, MAX2839_FT_5M },
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{ 5500000, MAX2839_FT_5_5M },
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{ 6000000, MAX2839_FT_6M },
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{ 7000000, MAX2839_FT_7M },
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{ 8000000, MAX2839_FT_8M },
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{ 9000000, MAX2839_FT_9M },
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{ 10000000, MAX2839_FT_10M },
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{ 12000000, MAX2839_FT_12M },
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{ 14000000, MAX2839_FT_14M },
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{ 15000000, MAX2839_FT_15M },
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{ 20000000, MAX2839_FT_20M },
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{ 24000000, MAX2839_FT_24M },
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{ 28000000, MAX2839_FT_28M },
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{ 0, 0 },
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};
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//clang-format on
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uint32_t max2839_set_lpf_bandwidth(max2839_driver_t* const drv, const uint32_t bandwidth_hz) {
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const max2839_ft_t* p = max2839_ft;
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while( p->bandwidth_hz != 0 ) {
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if( p->bandwidth_hz >= bandwidth_hz ) {
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break;
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}
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p++;
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}
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if( p->bandwidth_hz != 0 ) {
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set_MAX2839_FT(drv, p->ft);
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max2839_regs_commit(drv);
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}
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return p->bandwidth_hz;
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}
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bool max2839_set_lna_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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uint16_t val;
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// TODO: validate steps here
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switch(gain_db){
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case 40:
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val = MAX2839_LNAgain_MAX;
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break;
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case 32:
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val = MAX2839_LNAgain_M8;
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break;
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case 24:
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val = MAX2839_LNAgain_M16;
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break;
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case 8:
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val = MAX2839_LNAgain_M32;
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break;
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default:
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return false;
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}
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set_MAX2839_LNAgain(drv, val);
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max2839_reg_commit(drv, 1);
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return true;
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}
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bool max2839_set_vga_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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if( (gain_db & 0x1) || gain_db > 62) {/* 0b11111*2 */
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return false;
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}
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set_MAX2839_VGA(drv, 31-(gain_db >> 1) );
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max2839_reg_commit(drv, 5);
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return true;
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}
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bool max2839_set_txvga_gain(max2839_driver_t* const drv, const uint32_t gain_db) {
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uint16_t val=0;
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if(gain_db <16){
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val = 31-gain_db;
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val |= (1 << 5); // bit6: 16db
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} else{
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val = 31-(gain_db-16);
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}
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set_MAX2839_TXVGA_GAIN(drv, val);
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max2839_reg_commit(drv, 29);
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return true;
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}
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97
firmware/common/max2839.h
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97
firmware/common/max2839.h
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@ -0,0 +1,97 @@
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/*
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* Copyright 2012 Will Code? (TODO: Proper attribution)
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* Copyright 2014 Jared Boone <jared@sharebrained.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __MAX2839_H
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#define __MAX2839_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "gpio.h"
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#include "spi_bus.h"
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/* 32 registers, each containing 10 bits of data. */
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#define MAX2839_NUM_REGS 32
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#define MAX2839_DATA_REGS_MAX_VALUE 1024
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typedef enum {
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MAX2839_MODE_SHUTDOWN,
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MAX2839_MODE_CLKOUT,
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MAX2839_MODE_STANDBY,
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MAX2839_MODE_RX,
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MAX2839_MODE_TX,
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MAX2839_MODE_RX_CAL,
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MAX2839_MODE_TX_CAL,
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} max2839_mode_t;
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struct max2839_driver_t;
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typedef struct max2839_driver_t max2839_driver_t;
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struct max2839_driver_t {
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spi_bus_t* const bus;
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gpio_t gpio_enable;
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gpio_t gpio_rx_enable;
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gpio_t gpio_tx_enable;
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void (*target_init)(max2839_driver_t* const drv);
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void (*set_mode)(max2839_driver_t* const drv, const max2839_mode_t new_mode);
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max2839_mode_t mode;
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uint16_t regs[MAX2839_NUM_REGS];
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uint32_t regs_dirty;
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};
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/* Initialize chip. */
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extern void max2839_setup(max2839_driver_t* const drv);
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/* Read a register via SPI. Save a copy to memory and return
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* value. Mark clean. */
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extern uint16_t max2839_reg_read(max2839_driver_t* const drv, uint8_t r);
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/* Write value to register via SPI and save a copy to memory. Mark
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* clean. */
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extern void max2839_reg_write(max2839_driver_t* const drv, uint8_t r, uint16_t v);
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/* Write all dirty registers via SPI from memory. Mark all clean. Some
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* operations require registers to be written in a certain order. Use
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* provided routines for those operations. */
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extern void max2839_regs_commit(max2839_driver_t* const drv);
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max2839_mode_t max2839_mode(max2839_driver_t* const drv);
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void max2839_set_mode(max2839_driver_t* const drv, const max2839_mode_t new_mode);
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/* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
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extern void max2839_start(max2839_driver_t* const drv);
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extern void max2839_stop(max2839_driver_t* const drv);
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/* Set frequency in Hz. Frequency setting is a multi-step function
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* where order of register writes matters. */
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extern void max2839_set_frequency(max2839_driver_t* const drv, uint32_t freq);
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uint32_t max2839_set_lpf_bandwidth(
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max2839_driver_t* const drv,
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const uint32_t bandwidth_hz);
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bool max2839_set_lna_gain(max2839_driver_t* const drv, const uint32_t gain_db);
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bool max2839_set_vga_gain(max2839_driver_t* const drv, const uint32_t gain_db);
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bool max2839_set_txvga_gain(max2839_driver_t* const drv, const uint32_t gain_db);
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extern void max2839_tx(max2839_driver_t* const drv);
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extern void max2839_rx(max2839_driver_t* const drv);
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#endif // __MAX2839_H
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@ -54,9 +54,29 @@ __MREG__(MAX2839_RESERVED_6,4,1,2)
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__MREG__(MAX2839_LPF_CUTOFF,4,3,2)
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__MREG__(MAX2839_RESERVED_7,4,5,2)
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__MREG__(MAX2839_LPF_RF_BAND,4,9,4)
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#define MAX2839_FT_1_75M 0
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#define MAX2839_FT_2_5M 1
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#define MAX2839_FT_3_5M 2
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#define MAX2839_FT_5M 3
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#define MAX2839_FT_5_5M 4
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#define MAX2839_FT_6M 5
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#define MAX2839_FT_7M 6
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#define MAX2839_FT_8M 7
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#define MAX2839_FT_9M 8
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#define MAX2839_FT_10M 9
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#define MAX2839_FT_12M 10
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#define MAX2839_FT_14M 11
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#define MAX2839_FT_15M 12
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#define MAX2839_FT_20M 13
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#define MAX2839_FT_24M 14
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#define MAX2839_FT_28M 15
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/* REG 5 */
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__MREG__(MAX2839_LNA1gain_SPI,5,1,2)
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#define MAX2839_LNAgain_MAX 0b000 // Pad in 8dB steps, bits reversed
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#define MAX2839_LNAgain_M8 0b001
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#define MAX2839_LNAgain_M16 0b010
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#define MAX2839_LNAgain_M32 0b011
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__MREG__(MAX2839_Rx1_VGAgain,5,7,6)
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__MREG__(MAX2839_LPFblock_MODE,5,9,2)
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