Jared Boone d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
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This repository contains hardware designs and software for HackRF, a low cost, open source Software Defined Radio platform.

HackRF One

(photo by fd0 from https://github.com/fd0/hackrf-one-pictures)

principal author: Michael Ossmann mike@ossmann.com

http://greatscottgadgets.com/hackrf/

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