Jared Boone 9a53fd3a07 New CPLD .svf.
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
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This directory contains things shared by multiple HackRF firmware
implementations.