38 lines
1.1 KiB
Markdown
38 lines
1.1 KiB
Markdown
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CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either
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as all inputs or all outputs.
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Requirements
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============
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To build this VHDL project and produce an SVF file for flashing the CPLD:
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* Xilinx WebPACK 13.4 for Windows or Linux.
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* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
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in the "Device Models" Support Resources section of the CoolRunner-II
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Product Support & Documentation page. Only one file from the BSDL package is
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required, and the "program" script below expects it to be at the relative
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path "bsdl/xc2c/xc2c64.bsd".
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To program the SVF file into the CPLD:
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* Dangerous Prototypes Bus Blaster v2:
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* Configured with JTAGKey buffers.
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* Connected to CPLD JTAG signals on Jellybean.
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* urJTAG built with libftdi support.
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To Program
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==========
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./program
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...which connects to the Bus Blaster interface 0, sets the BSDL directory,
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detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf
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file to the CPLD.
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Usage:
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B1AUX9=0 control SGPIO0 to 15 as Input. B2AUX[1-16] => SGPIO[0-15]
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B1AUX9=1 control SGPIO0 to 15 as Output. SGPIO[0-15] => B2AUX[1-16]
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