Sojus07/hackrf
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Author SHA1 Message Date
Jared Boone
f51ee2dc61 Modified ldscripts to more accurately represent LPC4330 hardware. 
Moved M0 RAM from local to AHB.
Created separate region for sleep RAM.
 2013-12-07 15:29:50 -08:00
Jared Boone
34b01d89af Add SGPIO DMA configuration code. 2013-12-07 15:29:14 -08:00
Jared Boone
3e7ff530d7 Add GPDMA API. Should go in libopencm3 when it's more fleshed-out. 2013-12-07 15:28:59 -08:00
Jared Boone
5468a01a9b Forgot to include rf_path.h now that its pin setup is called from hackrf_core. 2013-11-21 10:23:53 -08:00
Jared Boone
b285b91e4c Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/hackrf_core.h
	firmware/common/rffc5071.c
 2013-11-20 18:43:40 -08:00
Jared Boone
62ab69c3d2 Giant .gitignore to knock out build files, Xilinx spew, and editor/OS turds. 2013-11-20 15:51:59 -08:00
Jared Boone
9db166427f Remove I2S pin definitions, since they're too specific for generic/shared HackRF code. 2013-11-20 15:46:53 -08:00
Jared Boone
f453e4c377 Bump libopencm3. 2013-11-20 15:44:15 -08:00
Jared Boone
986e4dec93 Massive rework of Makefile_inc.mk, to support building of heterogeneous (M4+M0) binaries, and easy switching between RAM and SPIFI-bootable builds. Constructive criticism welcome -- I'm sure there's better ways to do this. 2013-11-20 15:28:28 -08:00
Jared Boone
02ba23bf68 Fix broken sgpio-rx project, broken due to massive changes to how RF path and tuning is done. 2013-11-20 15:24:50 -08:00
Jared Boone
893c20e41f Fix naming problem with SGPIO test project. This is due to my use of VPATH in Makefile_inc.mk, which I'm starting to regret a little bit... 2013-11-20 15:24:14 -08:00
Jared Boone
552dbe4a6d Add sgpio.c to C files, now required for pin initialization. 2013-11-20 15:23:26 -08:00
Jared Boone
6a03f157ff With Makefile RAM/SPIFI option, remove/rework redundant "rom_to_ram" projects. 2013-11-20 15:21:40 -08:00
Jared Boone
c365d0a37e Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region. 2013-11-20 15:14:13 -08:00
Jared Boone
31a55d0e9b Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now... 2013-11-20 15:13:18 -08:00
Jared Boone
e29ec6b084 Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files. 2013-11-20 15:11:54 -08:00
Jared Boone
91a7ca4983 Fix return value on SGPIO decimation function. 2013-11-20 15:08:59 -08:00
Jared Boone
e3f9e204c1 Relocate SGPIO pin configuration -- it only needs to be done once. 2013-11-20 13:22:19 -08:00
Jared Boone
39276f162c Add M0 linker script. 2013-11-19 19:52:50 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller. 
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
 2013-11-19 19:52:06 -08:00
Jared Boone
24a8e2bdb5 Remove CPLD SVF file, as it's not used by anybody (as far as I know). 2013-11-19 19:45:36 -08:00
Michael Ossmann
5b14636c2c initial firmware support for HackRF One 2013-11-19 10:01:26 -07:00
Jared Boone
967e699815 Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values. 2013-11-17 22:23:08 -08:00
Michael Ossmann
a909ca641c moved GCK1 test point 2013-11-16 21:39:15 -07:00
Michael Ossmann
ca2162da29 forgot to save schematic 2013-11-16 21:26:07 -07:00
Michael Ossmann
95ffc704a1 P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28 2013-11-16 21:22:25 -07:00
Jared Boone
d006ec769c Updated CPLD bitstream with two's complement I/O and sample ordering fix. 2013-11-16 13:41:54 -08:00
Jared Boone
89eafaa79a Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this. 2013-11-16 13:32:41 -08:00
Jared Boone
7ef9c1e932 Slow down edges of data lines coming from CPLD. 2013-11-16 13:31:19 -08:00
Jared Boone
147f47a3f5 Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed. 
Do conversion from unsigned to two's-compliment inside FPGA.
 2013-11-16 13:29:00 -08:00
Jared Boone
9856ea3d14 Changes due to CGU header API changes. 2013-11-15 11:41:20 -08:00
Michael Ossmann
db3ef109fa forgot to save schematic when adding clock signals to header 2013-11-11 20:56:47 -07:00
Michael Ossmann
06f345239b silkscreen tweaks 2013-11-11 20:49:57 -07:00
Michael Ossmann
fecc7346b3 GND test points 2013-11-11 19:25:28 -07:00
Michael Ossmann
a8c2c0b6d1 more decoupling caps 2013-11-11 19:07:28 -07:00
Michael Ossmann
26104e6735 nudged some traces in the RF section 2013-11-11 18:48:39 -07:00
Michael Ossmann
c5533b3c96 reworked zones so LED signals do not cross power planes 2013-11-11 18:04:45 -07:00
Michael Ossmann
515b6973aa exposed GCK1, GCK2 on expansion P28 instead of extra CPLD pins. also ditched 1V8 on P30 2013-11-11 17:23:45 -07:00
Michael Ossmann
f576fc27f0 rerouted 1V8 2013-11-11 16:58:30 -07:00
Michael Ossmann
1b3da372b9 CPLD JTAG cleanup 2013-11-11 16:37:43 -07:00
Michael Ossmann
4577439912 keep GCK1 on front side 2013-11-11 16:32:37 -07:00
Michael Ossmann
174c3b427b still cleaning 2013-11-11 11:09:48 -07:00
Michael Ossmann
fbcc3b60ec still more clean-up 2013-11-11 10:57:08 -07:00
Michael Ossmann
923971402c a little more clean-up 2013-11-11 10:51:12 -07:00
Michael Ossmann
976096f019 a little clean-up 2013-11-11 10:25:46 -07:00
Michael Ossmann
f7e1b15cc9 more mounting holes 2013-11-11 10:04:29 -07:00
Michael Ossmann
20518a77d5 SPIFI test points 2013-11-10 23:17:48 -07:00
Michael Ossmann
5beef42bc5 track clean-up 2013-11-10 23:11:04 -07:00
Michael Ossmann
d6b7202e64 corner holes 2013-11-10 20:23:04 -07:00
Michael Ossmann
198bc7afeb TVS diodes for CLKIN and CLKOUT 2013-11-10 20:19:38 -07:00