4 Commits

Author	SHA1	Message	Date
TitanMKD	294e958472	sgpio_if (top.vhd) CPLD VHDL fix for IQ/aliasing problems for ADC. (cpldjtagprog => sgpio_if_xsvf.h updated to rebuild). ... usb_performance.c SGPIO IQ fix for ADC (QI->IQ) for new CPLD (use usb_performance_rom_to_ram version else there is some packet lost even at 10Mhz sampling rate => make -f Makefile_rom_to_ram.)	2013-04-04 19:43:30 +02:00
TitanMKD	fa47f8af8c	Fix for IQ problem for ADC: ... RX samples are ordered I0,Q1,I1,Q2,I2,... where they should be I0,Q0,I1,Q1,I2,Q2,... This fix also alias/ghost problems to be confirmed on other boards/more tests... Drawback now IQ is QI, will be fixed/swapped in LPC4330 SGPIO code.	2013-04-04 00:55:51 +02:00
Jared Boone	d68036f79d	Eliminate ill-conceived HOST_CLK from CPLD. ... Rearrange clocks to not use AC-coupled CLK1 from Si5351C. Move CODEC_CLK to GCLK1, CODEC_X2_CLK (now HOST_CLK, too) to GCLK2. Add trace on Jellybean PCB to connect GCLK2 to LPC4330 pin 56 (P1_12) -- a different SGPIO8.	2012-06-14 19:08:20 -07:00
Jared Boone	07b6f81a6c	Initial implementation of MAX5864 <-> SGPIO interface via Xilinx CoolRunner-II CPLD.	2012-06-09 22:02:45 -07:00