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283 Commits

Author SHA1 Message Date
Michael Ossmann
237df75789 extra clock after RFFC serial transactions, Jawbreaker RF switch control 2012-09-20 11:59:33 -06:00
Michael Ossmann
425a384832 Jawbreaker LPC crystal oscillator startup 2012-09-20 10:53:07 -06:00
Michael Ossmann
2c813ec41e Jawbreaker clock generator configuration 2012-09-19 13:43:16 -06:00
Michael Ossmann
7d0c572569 Jawbreaker mixer serial interface support 2012-09-19 11:55:24 -06:00
Jared Boone
c662309489 Hot steaming pile of in-progress USB test code. Eventually, this will morph into a proper stack. But first, to "make it work". 2012-09-11 11:36:30 -07:00
Jared Boone
ddd3796803 Makefile change to use RAM-only LDScript. 2012-09-11 11:33:26 -07:00
Jared Boone
af1281fdbe LDScript for RAM-only operation. (That's how I like to roll -- load RAM over SWD and execute.) 2012-09-11 11:33:07 -07:00
Jared Boone
7d942c86ac Exposing the delay() core function. 2012-09-11 11:32:20 -07:00
Jared Boone
f5d21b947b Changes to bit band API to make it more type-sane. 2012-09-11 11:31:49 -07:00
Jared Boone
ec0bbe53c4 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-09-11 09:51:51 -07:00
Will Code
d7a7825f85 Fix overflows in shifts, suppress warnings for temporarily unused variables. 2012-09-04 20:08:30 -04:00
Jared Boone
94cffa41e5 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-09-04 09:24:18 -07:00
Will Code
599acbe142 Driver for RFFC5071 2012-09-03 19:16:09 -04:00
Will Code
f595bd149b Error in bit shift 2012-09-03 19:15:49 -04:00
Jared Boone
8758bb05ba Merge branch 'master' of https://github.com/mossmann/hackrf 2012-08-25 15:02:27 -07:00
Michael Ossmann
f74dae180b sgpio-rx updates for testing with Lollipop 2012-08-24 13:57:27 -06:00
Michael Ossmann
bc102abd7e .gitignore files 2012-08-23 23:30:54 -06:00
Michael Ossmann
6d74a94e54 configure both mixers 2012-08-23 21:34:38 -06:00
Michael Ossmann
834b3aabd1 RFFC5071 integer tuning function 2012-08-23 16:30:45 -06:00
Michael Ossmann
344a2f2a83 more clock generator config fixes 2012-08-23 12:59:49 -06:00
Michael Ossmann
5364c91f7b hard coded 8 MHz baseband filter for now 2012-08-23 09:52:16 -06:00
Michael Ossmann
cbd2d98c7d fixed bad output spectrum. problem was P3 = 0 in si5351c pll, similar to commit b595de647077f208c534e4efc0bce92f25378fb8 2012-08-22 10:41:53 -06:00
Jared Boone
9f4f1d0b6b Bitband library, factored out of other code. 2012-07-31 22:07:08 -07:00
Jared Boone
2a6e3a89d3 USB performance test firmware project. It does absolutely nothing to start with, but at least the Makefile I just checked in won't blow up! :-) 2012-07-31 22:05:28 -07:00
Jared Boone
33617e6701 Makefile for all firmware projects. 
TODO: There's still something broken about the *_rom_to_ram projects, but I'm not sure what it is yet...
 2012-07-31 22:03:58 -07:00
Jared Boone
f0e4cffb87 Removed release_cpld_jtag_pins() and incorporated code into pin_setup(). 2012-07-31 22:03:01 -07:00
Jared Boone
79d352f17f Fixed Makefile breakage in blinky and blinky_rom_to_ram. 2012-07-31 21:39:43 -07:00
Jared Boone
72ee83eda9 Moving gpio_setup() / pin_setup() functions in separate projects to hackrf_core.h/c. 
Moved enable_1v8_power() and release_cpld_jtag_pins() to hackrf_core.h/c.
 2012-07-31 21:38:57 -07:00
Jared Boone
9a8e5dcdf0 Flip sense of capture clock on SGPIO, which seems to solve the RX data corruption issues. TODO: I wish I had more than empirical evidence that this fix is correct... 2012-07-24 13:31:57 -07:00
Jared Boone
c8c0028d27 Moved CGU peripheral and APB1 base clock configurations to before SSP1 configuration. 2012-07-24 13:29:54 -07:00
Jared Boone
3593bee128 Corrected typo regarding SGPIO external clock configuration. 2012-07-24 13:29:03 -07:00
Michael Ossmann
fea87d8de5 sgpio-rx test firmware 2012-07-23 15:35:44 -06:00
Jared Boone
9f334fc5f0 Simple support for MAX5864 configuration via SPI. 2012-07-19 14:57:06 -07:00
TitanMKD
fab51038c0 SGPIO Test with CPLD passthrough mode => work in progress because I have some hardware issues on my board. 
For details on Hardware issues see Test_SGPIO0_to15.pdf or Test_SGPIO0_to15.ods
 2012-07-15 18:17:27 +02:00
Michael Ossmann
a784812100 updated require connections 2012-06-25 23:36:09 -06:00
TitanMKD
988b3e3a49 Fixed simple systick example 2012-06-25 22:45:18 +02:00
TitanMKD
bb12d3f601 Example removed and replaced by startup_systick_perfo_rom_to_ram 2012-06-25 22:34:29 +02:00
TitanMKD
53c7fcf768 * Fixed linker script form SPIFI and RAM execution. 
* Added performance checks and results on SPIFI & SRAM code execution.
 2012-06-25 22:15:10 +02:00
TitanMKD
dfb38a5a59 Fix asm macro 2012-06-25 22:02:55 +02:00
Jared Boone
2e16f51252 Python program to verify logic on the Lollipop board. 2012-06-19 23:09:42 -07:00
Michael Ossmann
ba909c0fe5 MAX2837 TXVGA register bug fix 2012-06-18 17:32:23 -06:00
Jared Boone
72e3dc1e21 TX sample generation loop that outputs an eight-sample sine wave. (1.25MHz assuming 10MHz codec clock.) 2012-06-15 16:20:46 -07:00
Jared Boone
bab6ec5fef Move buffer allocation to before enabling CPLD I/O, so as not to mess up I/Q synchronization. 2012-06-15 16:16:05 -07:00
Jared Boone
e32a60495a Change initial TX output data to the neutral value (0x80). 2012-06-15 16:14:58 -07:00
Jared Boone
59a5b92300 Correct CPLD JTAG pin release code to properly tri-state the pins. 2012-06-15 16:13:17 -07:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
f0bf6dbf97 Merge branch 'master' of https://github.com/mossmann/hackrf 2012-06-15 15:11:16 -07:00
Michael Ossmann
10e20fbce2 cut out serial test and do some actual mixing 2012-06-14 22:00:27 -06:00
Michael Ossmann
b0ebd75188 two-clocks-while-ENX-high fix for write operations, various example PLL configs 2012-06-14 19:52:45 -06:00
Jared Boone
f53818a46f Additional calls to initialize SSP1, considering changes I committed minutes earlier. 2012-06-14 13:09:02 -07:00