7 Commits

Author	SHA1	Message	Date
Jared Boone	2f1eedcf23	CPLD: Tweak ISE tool settings for speed instead of density.	2019-01-18 16:10:21 -08:00
Jared Boone	60085e8892	CPLD: Set SLEW=SLOW as default, remove from UCF.	2019-01-16 18:09:00 -08:00
Jared Boone	9a66cefc81	CPLD: Set default IOSTANDARD to LVCMOS33, remove from UCF.	2019-01-16 18:06:01 -08:00
Jared Boone	f8b6e9145c	CPLD: Pull up HOST_SYNC signal, which is usually floating. ... HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady. In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.	2019-01-16 17:55:45 -08:00
Jared Boone	8e387e5489	CPLD: Update bitstream files with RX Q channel flip.	2014-08-11 13:02:14 -07:00
Jared Boone	572f2285f2	Let Xilinx ISE update some unimportant project file header stuff.	2014-01-11 15:17:47 -08:00
Michael Ossmann	9276b9e89a	moved cpld stuff out of hardware/jellybean where people would be unlikely to look for it	2013-05-18 09:48:37 -06:00