167 Commits

Author SHA1 Message Date
Michael Ossmann
1f73f2fd25 h1r9: add Si5351A support 2023-01-06 14:33:48 +00:00
Michael Ossmann
6d48671084 h1r9: initial GPIO definitions 2023-01-06 12:45:51 +00:00
Michael Ossmann
8aa79e9fe5 h1r9: use timer to detect external clock frequency 2023-01-06 12:45:46 +00:00
Michael Ossmann
173612ac77 add --led option to hackrf_debug
and corresponding changes to libhackrf and firmware
2022-12-18 07:22:17 -05:00
Michael Ossmann
b026c07000 firmware: fix duration of delay_us_at_mhz() 2022-09-26 16:43:43 -04:00
Michael Ossmann
06b9d7bee0 Clean up source code copyright notices. 2022-09-23 14:46:52 -04:00
Martin Ling
6d57709000 Move delay after enabling RF power to rad1o-specific code. 2022-09-19 10:46:01 +01:00
Martin Ling
c0d13de598 Add braces to all control statements without them. 2022-08-03 23:46:46 +01:00
Martin Ling
c3fdf402d7 Reformat all code to new clang-format standard. 2022-08-03 23:46:44 +01:00
Martin Ling
dbcc46d221 Mark code sections to be left alone by clang-format. 2022-08-03 23:03:15 +01:00
Martin Ling
b4c828915a Use an empty block for empty while loops. 2022-08-03 23:03:15 +01:00
Martin Ling
6b5193198b Realign GPIO assignments with spaces rather than tabs. 2022-08-03 23:03:15 +01:00
Martin Ling
405515d5b4 Implement NXP's recommended setup sequence for the PLL and M4 clock.
This follows the sequence described in:

UM10503 Rev 2.4 (Aug 2018), section 13.2.1.1, page 167
2022-06-13 16:49:45 +01:00
Martin Ling
273e6a1217 Add an accurate delay loop.
The existing 'delay' function is not calibrated to any specific measure
of time. Add a new function using a loop with a known cycle count, to
produce delays of a given duration at a given CPU clock speed.
2022-06-13 16:32:55 +01:00
Andreas Gibhardt
fc8b3c18d6 fix stream glitch on rate change 2021-12-02 16:27:43 +01:00
Schuyler St. Leger
9ee25ab48a operacake: add support for port switching using SCTimer
Based on Schuyler St. Leger's operacake-sctimer branch
2021-10-14 14:36:18 +01:00
Mike Walters
05b1650a6a Rename hackrf-ui.[ch]
Every other source file uses underscores! :(
2020-01-22 14:20:23 +00:00
Jared Boone
190c3972f4 Clock reference: Add UI hook. Simplify selection code. 2019-03-20 20:18:25 -07:00
Jared Boone
891eaa9e62 Clock reference: Return enum for selected clock source. 2019-03-20 14:38:18 -07:00
Jared Boone
dccb748216 PortaPack: Add check for PortaPack clock reference, use if present.
Wow, it takes a lot of ugly code to keep blinky happy...
2019-03-20 13:27:20 -07:00
Jared Boone
46fd11af5b Si5351C: Extract best block source function into hackrf_core.
It's not an Si5351C driver thing, but a HackRF thing. Also added a driver function to check if CLKIN signal is valid, and made use of it, instead of opaque register read code.
2019-03-20 11:16:44 -07:00
Dominic Spill
4fcfbec96a Merge pull request #601 from jboone/hygiene
rad1o: Remove extra(?) SCU setup. Cut & paste oops?
2019-03-06 17:32:35 -07:00
Dominic Spill
42c1a46bb3 Fix mismatched ifdefs of my making 2019-03-06 17:17:20 -07:00
Dominic Spill
e27038a098 Merge branch 'master' into cpld_sram_load 2019-03-04 12:40:14 +00:00
Dominic Spill
19f073fc5a Merge branch 'master' into hygiene 2019-03-03 22:29:12 +00:00
Dominic Spill
a4c1ab65c6 Merge pull request #602 from jboone/ui_restructuring
PortaPack and rad1o Ui restructuring, take 2
2019-03-03 22:27:57 +00:00
Jared Boone
f259c9aad6 PortaPack: Add HackRF One gates for PortaPack JTAG and OperaCake code.
I think these #defines might finally be the right shape...
2019-03-02 20:43:19 -08:00
Jared Boone
24fe561f3b rad1o: Remove extra(?) SCU setup. Cut & paste oops? 2019-03-02 14:23:36 -08:00
Jared Boone
8bc8bc13f0 PortaPack: Remove conditional PortaPack code.
TODO: DFU mode returns. I fear HackRF mode in PortaPack/HAVOC will not work.
2019-03-02 14:23:06 -08:00
Jared Boone
c32d57158a PortaPack: Remove weak UI functions, detect and return UI function table.
TODO: Side effect was that now blinky has a lot of unreasonable dependencies.
TODO: rad1o breakage is likely...
2019-03-02 14:23:06 -08:00
Jared Boone
75adda314e LED: Refactor halt function from CPLD update to core API.
Also call if CPLD load fails.
2019-03-02 14:19:21 -08:00
Dominic Spill
e12866f81e Remove PLL1 low speed settings (it's out of spec) 2019-02-11 16:38:07 -07:00
Jared Boone
65b41fb80e blinky: Remove dependency on CPLD JTAG API.
Shouldn't need that just to blink an LED!
2019-01-22 15:20:14 -08:00
Jared Boone
f60b2479fb JTAG: Restore CPLD pin config functions, leave pins in pull-only state when not actively operating. 2018-12-31 10:12:28 -08:00
Jared Boone
816d435dc5 Pin setup: Break out JTAG configuration, rework to consider PortaPack. 2018-12-27 20:33:33 -08:00
Jared Boone
bfd3b1b768 Set 1V8 enable state before configuring pin function or to output mode
...to avoid glitching 1V8 enable voltage.
2018-12-27 20:31:31 -08:00
Jared Boone
610e6b58cc Set VAA_ENABLE# state before setting GPIO to output.
...to avoid glitching the output voltage.
2018-12-27 20:29:25 -08:00
Jared Boone
5535cf059e Pin setup: Make GPIO direction reset the *first* step. 2018-12-27 20:26:55 -08:00
Jared Boone
88fb406a55 PortaPack: Conditionally claim JTAG pins in SCU #defines 2018-12-27 10:10:01 -08:00
Jared Boone
ccc86aad14 Add support for PortaPack user interface add-on board. 2018-08-01 21:05:10 -07:00
Michael Ossmann
991c5089a9 Merge branch 'glitch-fix' 2018-02-02 15:15:27 -07:00
Michael Ossmann
5d6667141e short pulses when enabling VAA to avoid a big voltage glitch 2018-01-28 16:24:48 -07:00
Michael Ossmann
b095c5326a eliminated minor glitch caused by enabling a GPIO output before setting its value 2018-01-28 16:16:35 -07:00
Dominic Spill
3f569a8ad4 hackrf_clock: Allow CLKOUT to be enabled / disabled
hackrf_clock -o 1 / hackrf_clock -o 0
2017-11-07 11:23:48 -07:00
schneider
1acd7ccf7c fix(rad1o): TX_RX_N is on GPIO1_11 2017-08-05 06:05:31 +02:00
schneider
4b0bb0ea55 refact(rad1o): Disable the CPU clock outputs in pin_setup() 2017-08-05 06:04:08 +02:00
Dominic Spill
90d3f7f293 Remove unused ARRAY_SIZE definition 2017-07-11 18:27:24 -06:00
Marco Bartolucci
a773b463cb cleanup 2017-05-16 15:37:27 +02:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00