h1r9: add Si5351A support
This commit is contained in:
Michael Ossmann
committed by
Mike Walters
Mike Walters
parent
6d48671084
commit
1f73f2fd25
@ -36,6 +36,7 @@
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#include "i2c_lpc.h"
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#include "cpld_jtag.h"
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#include "platform_detect.h"
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#include "clkin.h"
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/ccu.h>
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#include <libopencm3/lpc43xx/scu.h>
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@ -414,14 +415,26 @@ bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
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MSx_P2 = (128 * b) % c;
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MSx_P3 = c;
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/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
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si5351c_configure_multisynth(&clock_gen, 0, MSx_P1, MSx_P2, MSx_P3, 1);
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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/*
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* On HackRF One r9 all sample clocks are externally derived
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* from MS1/CLK1 operating at twice the sample rate.
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*/
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si5351c_configure_multisynth(&clock_gen, 1, MSx_P1, MSx_P2, MSx_P3, 0);
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} else {
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/*
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* On other platforms the clock generator produces three
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* different sample clocks, all derived from multisynth 0.
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*/
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/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
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si5351c_configure_multisynth(&clock_gen, 0, MSx_P1, MSx_P2, MSx_P3, 1);
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(&clock_gen, 1, 0, 0, 0, 0); //p1 doesn't matter
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(&clock_gen, 1, 0, 0, 0, 0); //p1 doesn't matter
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(&clock_gen, 2, 0, 0, 0, 0); //p1 doesn't matter
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(&clock_gen, 2, 0, 0, 0, 0); //p1 doesn't matter
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}
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if (streaming) {
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sgpio_cpld_stream_enable(&sgpio_config);
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@ -482,14 +495,38 @@ bool sample_rate_set(const uint32_t sample_rate_hz)
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return false;
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}
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/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
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si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1);
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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/*
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* On HackRF One r9 all sample clocks are externally derived
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* from MS1/CLK1 operating at twice the sample rate.
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*/
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si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 0);
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} else {
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/*
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* On other platforms the clock generator produces three
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* different sample clocks, all derived from multisynth 0.
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*/
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/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
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si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1);
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(&clock_gen, 1, p1, 0, 1, 0); //p1 doesn't matter
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(
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&clock_gen,
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1,
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p1,
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0,
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1,
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0); //p1 doesn't matter
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(&clock_gen, 2, p1, 0, 1, 0); //p1 doesn't matter
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(
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&clock_gen,
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2,
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p1,
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0,
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1,
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0); //p1 doesn't matter
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}
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return true;
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}
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@ -596,7 +633,12 @@ void cpu_clock_init(void)
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si5351c_configure_pll_multisynth(&clock_gen);
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/*
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* Clocks:
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* Clocks on HackRF One r9:
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* CLK0 -> MAX5864/CPLD/SGPIO (sample clocks)
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* CLK1 -> RFFC5072/MAX2837
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* CLK2 -> External Clock Output/LPC43xx (power down at boot)
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*
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* Clocks on other platforms:
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* CLK0 -> MAX5864/CPLD
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* CLK1 -> CPLD
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* CLK2 -> SGPIO
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@ -607,22 +649,33 @@ void cpu_clock_init(void)
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* CLK7 -> LPC43xx (uses a 12MHz crystal by default)
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*/
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/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
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si5351c_configure_multisynth(
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&clock_gen,
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4,
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20 * 128 - 512,
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0,
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1,
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0); /* 800/20 = 40MHz */
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/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
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si5351c_configure_multisynth(
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&clock_gen,
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5,
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20 * 128 - 512,
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0,
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1,
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0); /* 800/20 = 40MHz */
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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/* MS0/CLK0 is the reference for both RFFC5071 and MAX2837. */
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si5351c_configure_multisynth(
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&clock_gen,
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0,
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20 * 128 - 512,
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0,
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1,
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0); /* 800/20 = 40MHz */
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} else {
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/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
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si5351c_configure_multisynth(
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&clock_gen,
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4,
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20 * 128 - 512,
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0,
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1,
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0); /* 800/20 = 40MHz */
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/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
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si5351c_configure_multisynth(
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&clock_gen,
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5,
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20 * 128 - 512,
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0,
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1,
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0); /* 800/20 = 40MHz */
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}
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/* MS6/CLK6 is unused. */
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/* MS7/CLK7 is unused. */
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@ -766,6 +819,10 @@ void cpu_clock_init(void)
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// CCU2_CLK_APLL_CFG = 0;
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// CCU2_CLK_SDIO_CFG = 0;
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#endif
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkin_detect_init();
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}
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}
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clock_source_t activate_best_clock_source(void)
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@ -191,7 +191,7 @@ void si5351c_configure_clock_control(
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const enum pll_sources source)
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{
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uint8_t pll;
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uint8_t clk3_ctrl;
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uint8_t clkout_ctrl;
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#ifdef RAD1O
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(void) source;
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@ -201,31 +201,29 @@ void si5351c_configure_clock_control(
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#if (defined JAWBREAKER || defined HACKRF_ONE)
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if (source == PLL_SOURCE_CLKIN) {
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if (detected_platform() < BOARD_ID_HACKRF1_R9) {
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/* PLLB on CLKIN */
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pll = SI5351C_CLK_PLL_SRC_B;
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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/*
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* HackRF One r9 always uses PLL A on the XTAL input
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* but externally switches that input to CLKIN.
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*/
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pll = SI5351C_CLK_PLL_SRC_A;
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gpio_set(&gpio_h1r9_clkin_en);
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} else {
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/* PLLB on CLKIN */
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pll = SI5351C_CLK_PLL_SRC_B;
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}
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} else {
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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if (detected_platform() < BOARD_ID_HACKRF1_R9) {
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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gpio_clear(&gpio_h1r9_clkin_en);
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}
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}
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#endif
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if (clkout_enabled) {
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clk3_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) |
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clkout_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA);
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} else {
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clk3_ctrl = SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE;
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clkout_ctrl = SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE;
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}
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/* Clock to CPU is deactivated as it is not used and creates noise */
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@ -241,7 +239,7 @@ void si5351c_configure_clock_control(
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SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA),
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clk3_ctrl,
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clkout_ctrl,
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SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV,
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@ -249,18 +247,28 @@ void si5351c_configure_clock_control(
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA),
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SI5351C_CLK_POWERDOWN |
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SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,
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SI5351C_CLK_INT_MODE, /* not connected, but: PLL A int mode */
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SI5351C_CLK_POWERDOWN |
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SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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SI5351C_CLK_INT_MODE /* not connected, but: PLL B int mode */
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};
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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data[1] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC_A |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA);
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data[2] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC_A |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA);
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data[3] = clkout_ctrl;
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data[4] = SI5351C_CLK_POWERDOWN;
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data[5] = SI5351C_CLK_POWERDOWN;
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data[6] = SI5351C_CLK_POWERDOWN;
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}
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si5351c_write(drv, data, sizeof(data));
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}
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#define SI5351C_CLK_ENABLE(x) (0 << x)
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#define SI5351C_CLK_DISABLE(x) (1 << x)
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#define SI5351C_REG_OUTPUT_EN (3)
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#define SI5351C_REG_CLK3_CTRL (19)
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void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
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{
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@ -270,8 +278,19 @@ void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
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uint8_t value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_ENABLE(2) | SI5351C_CLK_ENABLE(4) | SI5351C_CLK_ENABLE(5) |
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SI5351C_CLK_DISABLE(6) | SI5351C_CLK_DISABLE(7);
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uint8_t clkout = 3;
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value |= (clkout_enabled) ? SI5351C_CLK_ENABLE(3) : SI5351C_CLK_DISABLE(3);
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/* HackRF One r9 has only three clock generator outputs. */
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkout = 2;
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value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_DISABLE(3) | SI5351C_CLK_DISABLE(4) |
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SI5351C_CLK_DISABLE(5) | SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_DISABLE(7);
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}
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value |= (clkout_enabled) ? SI5351C_CLK_ENABLE(clkout) :
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SI5351C_CLK_DISABLE(clkout);
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uint8_t data[] = {SI5351C_REG_OUTPUT_EN, value};
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si5351c_write(drv, data, sizeof(data));
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@ -325,8 +344,14 @@ void si5351c_clkout_enable(si5351c_driver_t* const drv, uint8_t enable)
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{
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clkout_enabled = (enable > 0);
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//FIXME this should be somewhere else
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uint8_t clkout = 3;
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/* HackRF One r9 has only three clock generator outputs. */
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkout = 2;
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}
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/* Configure clock to 10MHz */
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si5351c_configure_multisynth(drv, 3, 80 * 128 - 512, 0, 1, 0);
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si5351c_configure_multisynth(drv, clkout, 80 * 128 - 512, 0, 1, 0);
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si5351c_configure_clock_control(drv, active_clock_source);
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si5351c_enable_clock_outputs(drv);
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