Sojus07/hackrf
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36 Commits

Author SHA1 Message Date
Jared Boone
1723cd12a1 Oops, read PLL1 documentation again. Looks like FBSEL=1 is for "normal operation". So include that, but use DIRECT=1 to skip the PSEL divider (which would prevent us producing 204MHz from an in-spec PLL frequency). 2013-05-11 12:25:54 -07:00
Jared Boone
e065cdfe20 Slowed down edges on LED and power enable signals -- they don't need to be fast, and this *might* have a negligible but positive effect on noise. 2013-05-11 12:13:00 -07:00
Jared Boone
d9884af8b8 PLL1 was misconfigured to run at 408MHz (way out of spec) instead of 204MHz. Corrected this by using DIRECT=1 instead of FBSEL=1. 2013-05-11 12:11:37 -07:00
Jared Boone
a4a2a3d6ba Added SCU pinmux data for USB LEDs, configured USB LEDs to be outputs (not float). 2013-05-11 08:09:07 -07:00
TitanMKD
d509489fff ssp1_set_mode_max2837()/void ssp1_set_mode_max5864(void) SPI speed updated to 4.857MHz instead of 0.0498MHz 
To do test it to check there is no problem.
 2013-03-20 22:20:47 +01:00
Michael Ossmann
1a2f871520 moved set_freq out of hackrf_core to facilitate switchctrl fixes 2013-03-07 17:35:48 -07:00
Michael Ossmann
052d842f36 temporary fix for gpo/switchctrl. only works for TX 2013-03-07 16:56:44 -07:00
TitanMKD
e3784c886e set_freq for firmware & host. tested basicly checking with debugger value mhz/hz from host to fw. 2013-03-07 23:24:00 +01:00
TitanMKD
e2c05fbfe2 Draft in progress (not tested at all) set_freq(). 2013-02-26 00:17:18 +01:00
TitanMKD
d46a59fba3 Fix for LPC4330 MCU frequency to be set to 204MHz instead of 102MHz. 2012-11-26 23:41:13 +01:00
Jared Boone
549c943979 Add USB control of LPF baseband filter. 
Add max2837_set_lpf_bandwidth() function to choose available LPF filter bandwidth based on bandwidth in Hz.
Change configuration of MAX2837 to set LPF_EN and FT at max2837_setup(), not in max2837_rx() or max2837_tx() (which was overriding prior filter configuration).
 2012-10-17 17:00:36 -07:00
Jared Boone
9c4a0e94b0 Factor out sample_rate_set() from cpu_clock_init(). 
Implement switching between several supported sampling rates for Jellybean and Jawbreaker.
Commit bits of the Si5351C USB request support that I apparently missed in a prior commit.
 2012-10-17 16:57:26 -07:00
Jared Boone
7fdfde9314 Make use of i2c0_init() argument to control duty cycle, when APB1 clock shifts from IRC (~12MHz) to PLL1 (204MHz). 2012-10-17 11:48:35 -07:00
Jared Boone
63b1a25979 Consolidate a few clock setup tasks that repeat among many projects into cpu_clock_init(). 2012-10-17 11:45:30 -07:00
Jared Boone
685f5cdd6e More detail in comments about Jellybean/Lemondrop clock destinations. 2012-10-10 11:51:06 -07:00
Jared Boone
4f9a5a1ba4 Fix-ups to copyrights -- missing e-mail address and inconsistent formatting. 2012-10-06 19:14:55 -07:00
Jared Boone
a975fbc577 Replaced apparently incorrect PLL0USB MDIV and NP_DIV values with values straight out of the User Manual's table 94. 2012-09-27 19:29:43 -07:00
Jared Boone
aaaf14819a Move PLL1/M4 CLK up to full speed (204MHz) in two steps, according to UM chapter 11.2.1. 2012-09-27 18:58:00 -07:00
Jared Boone
776c502628 More tweaks related to CGU #define changes. 2012-09-27 17:55:54 -07:00
Jared Boone
416cdc6b20 Added missing hackrf_core pin_setup() and enable_1v8_power(), which have somehow gone missing. 2012-09-27 16:26:47 -07:00
Michael Ossmann
425a384832 Jawbreaker LPC crystal oscillator startup 2012-09-20 10:53:07 -06:00
Michael Ossmann
2c813ec41e Jawbreaker clock generator configuration 2012-09-19 13:43:16 -06:00
Michael Ossmann
7d0c572569 Jawbreaker mixer serial interface support 2012-09-19 11:55:24 -06:00
Michael Ossmann
344a2f2a83 more clock generator config fixes 2012-08-23 12:59:49 -06:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Jared Boone
f08fc3bb51 Pulled SSP1 configuration for MAX2837 into hackrf_core. Added SSP1 configuration for MAX5864. Added #defines for manipulating CS of both MAX parts. Changed a couple of #define names to be consistent with other names. Added explicit manipulation of MAX2837 CS via GPIO. 2012-06-14 13:06:10 -07:00
Michael Ossmann
ad080a355a pull request #10, resolved conflicts 2012-06-13 21:21:34 -06:00
Jared Boone
61b7b76912 OOPS. Missed changes from clock reconfiguration two commits (and five minutes) ago. 2012-06-13 17:58:14 -07:00
Michael Ossmann
056ddd0601 r divider configurable, added CLK5 for mixer reference input 2012-06-13 16:02:40 -06:00
TitanMKD
352b82f641 Fixed Clock Init (to be tested on other board). 2012-06-08 02:24:05 +02:00
Michael Ossmann
9a7219eb4d removed PLL1 stages as they no longer seem to be necessary since the power-down fix 2012-06-07 13:40:59 -06:00
Michael Ossmann
98b6e92f97 fixed PLL1 startup problem by not powering it down first 2012-06-07 13:28:47 -06:00
Michael Ossmann
d1d1434fed bring up PLL1 in stages 2012-06-07 12:00:30 -06:00
Michael Ossmann
aeced361cf migrated common stuff to libopencm3 2012-06-07 08:14:16 -06:00
TitanMKD
acc806d5ce * Add PIN_EN1V8 (1V8 work fine 1V8 LED is set to ON), and PIN_BOOT0, 1, 2 & 3(read only). 
* Fixed wait() by using volatile else the loop was removed by GCC.
Tested it with SPIFI work fine:
SPIFI tested with LPCXpresso+NXP LPC Link (from LPCXpresso Board LPC1769 Debugger)
 -> Program Flash with Flash Driver LPC1850A_4350A_SPIFI.cfx
     -> Select file: firmware\blinky\blinky.bin
     -> Base address 0x14000000 & option Erase only required pages
 2012-05-28 00:02:48 +02:00
Michael Ossmann
a748e31328 started firmware directory with some basic stuff 2012-05-21 11:33:46 -06:00