412 lines
12 KiB
C
412 lines
12 KiB
C
/*
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* Copyright 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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* Copyright 2013 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hackrf_core.h"
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#include "si5351c.h"
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#include "max2837.h"
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#include "rffc5071.h"
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#include <libopencm3/lpc43xx/i2c.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/ssp.h>
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void delay(uint32_t duration)
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{
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uint32_t i;
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for (i = 0; i < duration; i++)
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__asm__("nop");
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}
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bool sample_rate_set(const uint32_t sample_rate_hz) {
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#ifdef JELLYBEAN
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/* Due to design issues, Jellybean/Lemondrop frequency plan is limited.
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* Long version of the story: The MAX2837 reference frequency
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* originates from the same PLL as the sample clocks, and in order to
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* keep the sample clocks in phase and keep jitter noise down, the MAX2837
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* and sample clocks must be integer-related.
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*/
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uint32_t r_div_sample = 2;
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uint32_t r_div_sgpio = 1;
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switch( sample_rate_hz ) {
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case 5000000:
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r_div_sample = 3; /* 800 MHz / 20 / 8 = 5 MHz */
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r_div_sgpio = 2; /* 800 MHz / 20 / 4 = 10 MHz */
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break;
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case 10000000:
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r_div_sample = 2; /* 800 MHz / 20 / 4 = 10 MHz */
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r_div_sgpio = 1; /* 800 MHz / 20 / 2 = 20 MHz */
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break;
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case 20000000:
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r_div_sample = 1; /* 800 MHz / 20 / 2 = 20 MHz */
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r_div_sgpio = 0; /* 800 MHz / 20 / 1 = 40 MHz */
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break;
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default:
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return false;
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}
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/* NOTE: Because MS1, 2, 3 outputs are slaved to PLLA, the p1, p2, p3
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* values are irrelevant. */
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/* MS0/CLK1 is the source for the MAX5864 codec. */
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si5351c_configure_multisynth(1, 4608, 0, 1, r_div_sample);
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/* MS0/CLK2 is the source for the CPLD codec clock (same as CLK1). */
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si5351c_configure_multisynth(2, 4608, 0, 1, r_div_sample);
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/* MS0/CLK3 is the source for the SGPIO clock. */
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si5351c_configure_multisynth(3, 4608, 0, 1, r_div_sgpio);
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return true;
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#endif
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#ifdef JAWBREAKER
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uint32_t p1 = 4608;
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switch(sample_rate_hz) {
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case 5000000:
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p1 = 9728; // 800MHz / 80 = 10 MHz (SGPIO), 5 MHz (codec)
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break;
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case 10000000:
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p1 = 4608; // 800MHz / 40 = 20 MHz (SGPIO), 10 MHz (codec)
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break;
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case 12500000:
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p1 = 3584; // 800MHz / 32 = 25 MHz (SGPIO), 12.5 MHz (codec)
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break;
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case 16000000:
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p1 = 2688; // 800MHz / 25 = 32 MHz (SGPIO), 16 MHz (codec)
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break;
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case 20000000:
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p1 = 2048; // 800MHz / 20 = 40 MHz (SGPIO), 20 MHz (codec)
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break;
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default:
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return false;
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}
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/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
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si5351c_configure_multisynth(0, p1, 0, 1, 1);
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/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
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si5351c_configure_multisynth(1, p1, 0, 1, 0);
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/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
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si5351c_configure_multisynth(2, p1, 0, 1, 0);
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/* MS0/CLK3 is the source for the external clock output. */
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si5351c_configure_multisynth(3, p1, 0, 1, 0);
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return true;
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#endif
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}
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bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
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return max2837_set_lpf_bandwidth(bandwidth_hz);
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}
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/* clock startup for Jellybean with Lemondrop attached */
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void cpu_clock_init(void)
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{
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/* use IRC as clock source for APB1 (including I2C0) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
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i2c0_init(15);
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si5351c_disable_all_outputs();
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si5351c_disable_oeb_pin_control();
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si5351c_power_down_all_clocks();
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si5351c_set_crystal_configuration();
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si5351c_enable_xo_and_ms_fanout();
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si5351c_configure_pll_sources_for_xtal();
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si5351c_configure_pll1_multisynth();
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#ifdef JELLYBEAN
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/*
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* Jellybean/Lemondrop clocks:
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* CLK0 -> MAX2837
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* CLK1 -> MAX5864/CPLD.GCLK0
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* CLK2 -> CPLD.GCLK1
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* CLK3 -> CPLD.GCLK2
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* CLK4 -> LPC4330
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* CLK5 -> RFFC5072
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* CLK6 -> extra
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* CLK7 -> extra
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*/
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/* MS0/CLK0 is the source for the MAX2837 clock input. */
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si5351c_configure_multisynth(0, 2048, 0, 1, 0); /* 40MHz */
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/* MS4/CLK4 is the source for the LPC43xx microcontroller. */
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si5351c_configure_multisynth(4, 8021, 0, 3, 0); /* 12MHz */
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/* MS5/CLK5 is the source for the RFFC5071 mixer. */
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si5351c_configure_multisynth(5, 1536, 0, 1, 0); /* 50MHz */
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#endif
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#ifdef JAWBREAKER
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/*
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* Jawbreaker clocks:
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* CLK0 -> MAX5864/CPLD
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* CLK1 -> CPLD
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* CLK2 -> SGPIO
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* CLK3 -> external clock output
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* CLK4 -> RFFC5072
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* CLK5 -> MAX2837
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* CLK6 -> none
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* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
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*/
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/* MS4/CLK4 is the source for the RFFC5071 mixer. */
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si5351c_configure_multisynth(4, 1536, 0, 1, 0); /* 50MHz */
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/* MS5/CLK5 is the source for the MAX2837 clock input. */
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si5351c_configure_multisynth(5, 2048, 0, 1, 0); /* 40MHz */
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/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
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//si5351c_configure_multisynth(7, 8021, 0, 3, 0); /* 12MHz */
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#endif
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/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
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sample_rate_set(10000000);
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si5351c_configure_clock_control();
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si5351c_enable_clock_outputs();
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//FIXME disable I2C
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/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
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i2c0_init(255);
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/*
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* 12MHz clock is entering LPC XTAL1/OSC input now. On
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* Jellybean/Lemondrop, this is a signal from the clock generator. On
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* Jawbreaker, there is a 12 MHz crystal at the LPC.
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* Set up PLL1 to run from XTAL1 input.
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*/
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//FIXME a lot of the details here should be in a CGU driver
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#ifdef JELLYBEAN
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/* configure xtal oscillator for external clock input signal */
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CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
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#endif
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/* set xtal oscillator to low frequency mode */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
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/* power on the oscillator and wait until stable */
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CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE;
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/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
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CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for APB1 */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
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/* use XTAL_OSC as clock source for PLL1 */
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/* Start PLL1 at 12MHz * 17 / (2+2) = 51MHz. */
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CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(1)
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| CGU_PLL1_CTRL_NSEL(0)
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| CGU_PLL1_CTRL_MSEL(16)
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| CGU_PLL1_CTRL_PD;
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/* power on PLL1 and wait until stable */
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CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_PD;
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
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/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
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CGU_BASE_M4_CLK = CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Move PLL1 up to 12MHz * 17 = 204MHz. */
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CGU_PLL1_CTRL = CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL)
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| CGU_PLL1_CTRL_PSEL(0)
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| CGU_PLL1_CTRL_NSEL(0)
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| CGU_PLL1_CTRL_MSEL(16)
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| CGU_PLL1_CTRL_FBSEL;
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/* wait until stable */
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while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));
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/* use XTAL_OSC as clock source for PLL0USB */
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CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
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| CGU_PLL0USB_CTRL_AUTOBLOCK
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| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
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while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
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/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
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/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
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CGU_PLL0USB_MDIV = 0x06167FFA;
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CGU_PLL0USB_NP_DIV = 0x00302062;
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CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
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| CGU_PLL0USB_CTRL_DIRECTI
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| CGU_PLL0USB_CTRL_DIRECTO
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| CGU_PLL0USB_CTRL_CLKEN);
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/* power on PLL0USB and wait until stable */
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CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD;
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while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
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/* use PLL0USB as clock source for USB0 */
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CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
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| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
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/* Switch peripheral clock over to use PLL1 (204MHz) */
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CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
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| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
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/* Switch APB1 clock over to use PLL1 (204MHz) */
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CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
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| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
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}
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void ssp1_init(void)
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{
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/*
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* Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
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* SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
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*/
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scu_pinmux(SCU_AD_CS, SCU_GPIO_FAST);
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GPIO_SET(PORT_AD_CS) = PIN_AD_CS;
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GPIO_DIR(PORT_AD_CS) |= PIN_AD_CS;
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scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
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GPIO_SET(PORT_XCVR_CS) = PIN_XCVR_CS;
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GPIO_DIR(PORT_XCVR_CS) |= PIN_XCVR_CS;
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/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
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scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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}
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void ssp1_set_mode_max2837(void)
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{
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/* FIXME speed up once everything is working reliably */
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/*
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// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 32;
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const uint8_t clock_prescale_rate = 128;
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*/
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// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 21;
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const uint8_t clock_prescale_rate = 2;
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ssp_init(SSP1_NUM,
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SSP_DATA_16BITS,
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SSP_FRAME_SPI,
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SSP_CPOL_0_CPHA_0,
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serial_clock_rate,
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clock_prescale_rate,
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SSP_MODE_NORMAL,
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SSP_MASTER,
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SSP_SLAVE_OUT_ENABLE);
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}
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void ssp1_set_mode_max5864(void)
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{
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/* FIXME speed up once everything is working reliably */
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/*
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// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 32;
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const uint8_t clock_prescale_rate = 128;
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*/
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// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 21;
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const uint8_t clock_prescale_rate = 2;
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ssp_init(SSP1_NUM,
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SSP_DATA_8BITS,
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SSP_FRAME_SPI,
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SSP_CPOL_0_CPHA_0,
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serial_clock_rate,
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clock_prescale_rate,
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SSP_MODE_NORMAL,
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SSP_MASTER,
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SSP_SLAVE_OUT_ENABLE);
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}
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void pin_setup(void) {
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/* Release CPLD JTAG pins */
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scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
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scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
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GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
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GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
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GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
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GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
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/* Configure SCU Pin Mux as GPIO */
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scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
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scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
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/* Configure USB indicators */
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scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
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scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
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/* Configure all GPIO as Input (safe state) */
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GPIO0_DIR = 0;
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GPIO1_DIR = 0;
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GPIO2_DIR = 0;
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GPIO3_DIR = 0;
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GPIO4_DIR = 0;
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GPIO5_DIR = 0;
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GPIO6_DIR = 0;
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GPIO7_DIR = 0;
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/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
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GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
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/* GPIO3[6] on P6_10 as output. */
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GPIO3_DIR |= PIN_EN1V8;
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/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
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scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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}
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void enable_1v8_power(void) {
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gpio_set(PORT_EN1V8, PIN_EN1V8);
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}
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