Sojus07/hackrf
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152 Commits

Author SHA1 Message Date
Schuyler St. Leger
9ee25ab48a operacake: add support for port switching using SCTimer 
Based on Schuyler St. Leger's operacake-sctimer branch
 2021-10-14 14:36:18 +01:00
Mike Walters
05b1650a6a Rename hackrf-ui.[ch] 
Every other source file uses underscores! :(
 2020-01-22 14:20:23 +00:00
Jared Boone
190c3972f4 Clock reference: Add UI hook. Simplify selection code. 2019-03-20 20:18:25 -07:00
Jared Boone
891eaa9e62 Clock reference: Return enum for selected clock source. 2019-03-20 14:38:18 -07:00
Jared Boone
dccb748216 PortaPack: Add check for PortaPack clock reference, use if present. 
Wow, it takes a lot of ugly code to keep blinky happy...
 2019-03-20 13:27:20 -07:00
Jared Boone
46fd11af5b Si5351C: Extract best block source function into hackrf_core. 
It's not an Si5351C driver thing, but a HackRF thing. Also added a driver function to check if CLKIN signal is valid, and made use of it, instead of opaque register read code.
 2019-03-20 11:16:44 -07:00
Dominic Spill
4fcfbec96a Merge pull request #601 from jboone/hygiene 
rad1o: Remove extra(?) SCU setup. Cut & paste oops?
 2019-03-06 17:32:35 -07:00
Dominic Spill
42c1a46bb3 Fix mismatched ifdefs of my making 2019-03-06 17:17:20 -07:00
Dominic Spill
e27038a098 Merge branch 'master' into cpld_sram_load 2019-03-04 12:40:14 +00:00
Dominic Spill
19f073fc5a Merge branch 'master' into hygiene 2019-03-03 22:29:12 +00:00
Dominic Spill
a4c1ab65c6 Merge pull request #602 from jboone/ui_restructuring 
PortaPack and rad1o Ui restructuring, take 2
 2019-03-03 22:27:57 +00:00
Jared Boone
f259c9aad6 PortaPack: Add HackRF One gates for PortaPack JTAG and OperaCake code. 
I think these #defines might finally be the right shape...
 2019-03-02 20:43:19 -08:00
Jared Boone
24fe561f3b rad1o: Remove extra(?) SCU setup. Cut & paste oops? 2019-03-02 14:23:36 -08:00
Jared Boone
8bc8bc13f0 PortaPack: Remove conditional PortaPack code. 
TODO: DFU mode returns. I fear HackRF mode in PortaPack/HAVOC will not work.
 2019-03-02 14:23:06 -08:00
Jared Boone
c32d57158a PortaPack: Remove weak UI functions, detect and return UI function table. 
TODO: Side effect was that now blinky has a lot of unreasonable dependencies.
TODO: rad1o breakage is likely...
 2019-03-02 14:23:06 -08:00
Jared Boone
75adda314e LED: Refactor halt function from CPLD update to core API. 
Also call if CPLD load fails.
 2019-03-02 14:19:21 -08:00
Dominic Spill
e12866f81e Remove PLL1 low speed settings (it's out of spec) 2019-02-11 16:38:07 -07:00
Jared Boone
65b41fb80e blinky: Remove dependency on CPLD JTAG API. 
Shouldn't need that just to blink an LED!
 2019-01-22 15:20:14 -08:00
Jared Boone
f60b2479fb JTAG: Restore CPLD pin config functions, leave pins in pull-only state when not actively operating. 2018-12-31 10:12:28 -08:00
Jared Boone
816d435dc5 Pin setup: Break out JTAG configuration, rework to consider PortaPack. 2018-12-27 20:33:33 -08:00
Jared Boone
bfd3b1b768 Set 1V8 enable state before configuring pin function or to output mode 
...to avoid glitching 1V8 enable voltage.
 2018-12-27 20:31:31 -08:00
Jared Boone
610e6b58cc Set VAA_ENABLE# state before setting GPIO to output. 
...to avoid glitching the output voltage.
 2018-12-27 20:29:25 -08:00
Jared Boone
5535cf059e Pin setup: Make GPIO direction reset the *first* step. 2018-12-27 20:26:55 -08:00
Jared Boone
88fb406a55 PortaPack: Conditionally claim JTAG pins in SCU #defines 2018-12-27 10:10:01 -08:00
Jared Boone
ccc86aad14 Add support for PortaPack user interface add-on board. 2018-08-01 21:05:10 -07:00
Michael Ossmann
991c5089a9 Merge branch 'glitch-fix' 2018-02-02 15:15:27 -07:00
Michael Ossmann
5d6667141e short pulses when enabling VAA to avoid a big voltage glitch 2018-01-28 16:24:48 -07:00
Michael Ossmann
b095c5326a eliminated minor glitch caused by enabling a GPIO output before setting its value 2018-01-28 16:16:35 -07:00
Dominic Spill
3f569a8ad4 hackrf_clock: Allow CLKOUT to be enabled / disabled 
hackrf_clock -o 1 / hackrf_clock -o 0
 2017-11-07 11:23:48 -07:00
schneider
1acd7ccf7c fix(rad1o): TX_RX_N is on GPIO1_11 2017-08-05 06:05:31 +02:00
schneider
4b0bb0ea55 refact(rad1o): Disable the CPU clock outputs in pin_setup() 2017-08-05 06:04:08 +02:00
Dominic Spill
90d3f7f293 Remove unused ARRAY_SIZE definition 2017-07-11 18:27:24 -06:00
Marco Bartolucci
a773b463cb cleanup 2017-05-16 15:37:27 +02:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation 
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
 2017-05-16 11:39:44 +02:00
Marco Bartolucci
747d8e2278 Removed decimation in CPLD 2017-05-15 12:56:51 +02:00
Dominic Spill
8b853266ef Power down CLK3 (CLKOUT) at boot, don't reset it when clocks are reset 2017-02-28 15:26:43 -07:00
Dominic Spill
e7f890e0c2 Merge branch 'mossmann-master' into firmware_cleanup 2017-02-22 12:10:42 -07:00
Dominic Spill
acaf0d192c Change RFFC5071 clock from 40MHz to 50MHz and invert it 
Now the MAX2837 and RFFC5071 clocks are out of phase with each other
Hopefully this reduces some noise
 2017-02-21 17:56:37 -07:00
Dominic Spill
3eb00ed0df Disable CLK7 and power down CLK6/7 to reduce emissions 2017-02-20 12:34:35 -07:00
schneider
d4c69890b5 fix(rad1o): Restore old clock behaviour for now. 2017-02-19 01:39:51 +01:00
Dominic Spill
a4036eab76 Remove last mentions of Jellybean 2017-02-16 18:03:32 -07:00
Dominic Spill
c6be7dea3e Fix build warnings for unused GPIO pins 2017-02-14 21:34:20 -07:00
Dominic Spill
49257e60e3 Remove Jellybean support from firmware 
- nobody has a jellybean board
 2017-02-14 21:33:52 -07:00
schneider42
4117cd3903 Merge branch 'master' into rad1o 2017-02-11 18:02:51 +01:00
Dominic Spill
c0396ea2fb Reenable some clocks so that HackRF boots 2017-02-10 10:29:54 -07:00
Dominic Spill
2163ebac9c Power down or disable all clocks that we aren't using 2017-02-09 21:23:58 -07:00
Dominic Spill
3de6d2d360 Disable EMC clock 2017-02-09 16:34:57 -07:00
schneider
c0c0fab368 chore(rad1o): White space fixes and cleanup 2017-02-03 19:27:19 +01:00
schneider
642feac51e Merge remote-tracking branch 'mossmann/master' into opera-merge 
Conflicts:
	firmware/common/hackrf_core.c
	firmware/common/rf_path.c
	firmware/hackrf-common.cmake
	firmware/hackrf_usb/hackrf_usb.c
	firmware/hackrf_usb/usb_api_transceiver.c
	host/hackrf-tools/src/hackrf_transfer.c
 2017-01-28 23:46:43 +01:00
schneider
9d8890ae62 fix(rad1o): gpio cleanup 2017-01-27 21:42:48 +01:00