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1162 Commits

Author SHA1 Message Date
Jared Boone
f259c9aad6 PortaPack: Add HackRF One gates for PortaPack JTAG and OperaCake code. 
I think these #defines might finally be the right shape...
 2019-03-02 20:43:19 -08:00
Jared Boone
24fe561f3b rad1o: Remove extra(?) SCU setup. Cut & paste oops? 2019-03-02 14:23:36 -08:00
Jared Boone
4fefd829ba CMake: Fix blinky and rad1o dependencies and PortaPack-related breakage. 2019-03-02 14:23:06 -08:00
Jared Boone
8bc8bc13f0 PortaPack: Remove conditional PortaPack code. 
TODO: DFU mode returns. I fear HackRF mode in PortaPack/HAVOC will not work.
 2019-03-02 14:23:06 -08:00
Jared Boone
c32d57158a PortaPack: Remove weak UI functions, detect and return UI function table. 
TODO: Side effect was that now blinky has a lot of unreasonable dependencies.
TODO: rad1o breakage is likely...
 2019-03-02 14:23:06 -08:00
Jared Boone
36cca31260 UI: Move ui_portapack.* to common. 
Otherwise blinky won't build.
TODO: Tried to tease apart all the dependencies to get blinky to build without, but it's such a twisted knot...
 2019-03-02 14:23:06 -08:00
Jared Boone
9ba4e50ee1 CPLD tool: Fix --checksum breakage. 2019-03-02 14:19:21 -08:00
Jared Boone
057b9273d5 CPLD tool: Rename to cpld_bitstream.py 2019-03-02 14:19:21 -08:00
Jared Boone
75adda314e LED: Refactor halt function from CPLD update to core API. 
Also call if CPLD load fails.
 2019-03-02 14:19:21 -08:00
Jared Boone
afb55e18dd CPLD: Load bitstream to SRAM at start-up. 2019-03-02 14:19:21 -08:00
Jared Boone
e7424dfcdc CPLD tool: Tweaks to produce cleaner program and verify structs. 2019-03-02 14:18:29 -08:00
Jared Boone
9aa3a78d78 CPLD tool: Add code generation, more bitstream checks. 
Code is now generated from programming block, checked against verify block, and also provides mask for verification process.
 2019-03-02 14:18:29 -08:00
Jared Boone
f70186644c CPLD tool: Add checksum and code generation mode flags. 2019-03-02 14:18:29 -08:00
Jared Boone
5695f29c8d CPLD tool: Add arguments help. 2019-03-02 14:18:29 -08:00
Jared Boone
0b4c714e0d CPLD tool: Remove commented code. 2019-03-02 14:18:29 -08:00
Jared Boone
30cd9586de CPLD tool: Flag to use crcmod library. 2019-03-02 14:18:29 -08:00
Jared Boone
fd1e5e77bf CPLD tool: Move imports to smallest scopes. 2019-03-02 14:18:29 -08:00
Jared Boone
20975e9313 CPLD: Tool argument parsing. 2019-03-02 14:18:29 -08:00
Jared Boone
d60389445d CPLD: Extract library code from CRC tool. 2019-03-02 14:18:29 -08:00
Jared Boone
257dbc749f CPLD: Checksum tool. 2019-03-02 14:18:29 -08:00
Dominic Spill
e12866f81e Remove PLL1 low speed settings (it's out of spec) 2019-02-11 16:38:07 -07:00
Dominic Spill
b701579906 Allow portapack and opera cake to coexist and still enable the PP UI 
The side effect of this is to disable GPIO mode for OC, but I2C still
works
Using both addons together is super unlikely
 2019-02-01 12:04:40 -07:00
Dominic Spill
4507130608 Merge pull request #584 from jboone/cpld_checksum 
Cpld checksum
 2019-01-31 15:16:05 -07:00
Jared Boone
fa2a9acd1a USB: initial CPLD checksum API support. 2019-01-31 21:19:21 +00:00
Jared Boone
499ac3ad4a PortaPack: Move UI code to hackrf_usb project. 
Was in common/ and in the common CMake file, which meant it was being included in the blinky project, which was unnecessary.
 2019-01-31 09:37:48 +00:00
Jared Boone
7b86403ce8 PortaPack: If hardware not detected, try to init OperaCake. 2019-01-31 09:24:59 +00:00
Dominic Spill
bc2b8568a0 Merge branch 'master' of https://github.com/jboone/hackrf into jboone-master 2019-01-30 15:33:16 -07:00
Dominic Spill
31079258e9 Workaround for avoiding conflicting libopencm3 targets 2019-01-30 15:29:17 -07:00
Jared Boone
1820c67aee PortaPack: Add build option info to firmware README 2019-01-30 22:17:36 +00:00
Dominic Spill
62efaf5ddb Merge branch 'master' of https://github.com/jboone/hackrf into jboone-master 2019-01-30 11:47:30 -07:00
Jared Boone
e433bee0b8 CMake: Move libopencm3 dependency out of CMake include file. 
Don't declare the libopencm3 target once from each project subdirectory. CMake will complain terribly.
 2019-01-22 15:21:43 -08:00
Jared Boone
65b41fb80e blinky: Remove dependency on CPLD JTAG API. 
Shouldn't need that just to blink an LED!
 2019-01-22 15:20:14 -08:00
Jared Boone
77e4cfe992 Merge remote-tracking branch 'jboone/cpld_fixes' 2019-01-21 17:37:48 -08:00
Jared Boone
f22fcd6083 CPLD: Finish fixing up timing re-validation for RX and TX. 2019-01-21 16:19:41 -08:00
Jared Boone
2f1eedcf23 CPLD: Tweak ISE tool settings for speed instead of density. 2019-01-18 16:10:21 -08:00
Jared Boone
d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO 
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
 2019-01-18 16:09:14 -08:00
Jared Boone
fd7b64d83c CPLD: Add files for making bitstreams via Makefile. 2019-01-18 12:11:32 -08:00
Jared Boone
60085e8892 CPLD: Set SLEW=SLOW as default, remove from UCF. 2019-01-16 18:09:00 -08:00
Jared Boone
9a66cefc81 CPLD: Set default IOSTANDARD to LVCMOS33, remove from UCF. 2019-01-16 18:06:01 -08:00
Jared Boone
f8b6e9145c CPLD: Pull up HOST_SYNC signal, which is usually floating. 
HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady.

In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.
 2019-01-16 17:55:45 -08:00
Jared Boone
3932c5694e PortaPack: Add .SVF of current JEDEC bitstream file. 
PortaPack build consumes this file to embed the bitstream into the firmware.
 2019-01-15 15:31:53 -08:00
Jared Boone
97806e8159 PortaPack: Build DFU binary without forcing serial number to "RunningFromRAM". 
This was causing problems for HackRF mode, where some host PC software was depending on a valid serial number.
 2019-01-15 11:31:39 -08:00
Jared Boone
909066cdf8 PortaPack: Replace OperaCake handlers, they were tripping up host tools. Skip operacake_init if PortaPack compiled in, letting operacake_boards be all zero. Should be safe, right? 2019-01-14 20:42:39 -08:00
Jared Boone
07f370bfba PortaPack: Silence warnings about unused functions/variables I'm liable to use soon. 
I don't like the __attribute__((unused)) markup, but woud rather not delete or comment out the code.
 2019-01-09 15:48:59 -08:00
Jared Boone
e87b3f4fea PortaPack: Address some unused variable/function warnings. 2019-01-09 15:30:24 -08:00
Jared Boone
e05677ab0d OperaCake: Bring together with PortaPack code. 
The plan is to have them coexist in the firmware binary, even if the hardware is mutually exclusive at runtime.
 2019-01-07 15:35:41 -08:00
Jared Boone
5e88bb8565 USB: Set Opera Cake USB handlers to null unless hardware is detected. 2019-01-07 15:30:32 -08:00
Jared Boone
0666dc961d USB: Bring in constants from host source code. 
TODO: Deduplicate this when I'm not feeling so lazy.
 2019-01-07 15:29:51 -08:00
Jared Boone
c7d761089f USB: Make vendor request handler table read/write (not const). 2019-01-07 15:29:18 -08:00
Dominic Spill
90d4014859 SPI flash: check busy flag is clear BEFORE enabling writes 2019-01-04 19:58:04 -07:00