Sojus07/hackrf
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52 Commits

Author SHA1 Message Date
Michael Ossmann
ff4e1107f3 h1r9: fix clkout PLL source bug 2023-01-06 14:33:56 +00:00
Michael Ossmann
50a2e9dd56 h1r9: update clock drive strength for spin C 2023-01-06 14:33:56 +00:00
Michael Ossmann
eb8ed45f9a h1r9: adjust PLLA according to source frequency 2023-01-06 14:33:53 +00:00
Michael Ossmann
a72f084ff0 h1r9: fix CLKOUT_EN pin setup 2023-01-06 14:33:53 +00:00
Michael Ossmann
1f73f2fd25 h1r9: add Si5351A support 2023-01-06 14:33:48 +00:00
Michael Ossmann
6d48671084 h1r9: initial GPIO definitions 2023-01-06 12:45:51 +00:00
Michael Ossmann
06b9d7bee0 Clean up source code copyright notices. 2022-09-23 14:46:52 -04:00
Michael Ossmann
2104291594 firmware: use consistent clock source 
CLKOUT now switches to the active clock source whenever the internal
clocks change source. It previously did so only when (re)enabled.
 2022-09-10 06:54:51 -04:00
Martin Ling
c0d13de598 Add braces to all control statements without them. 2022-08-03 23:46:46 +01:00
Martin Ling
c3fdf402d7 Reformat all code to new clang-format standard. 2022-08-03 23:46:44 +01:00
gozu42
4d0ea285b1 keep clkout state over general clock reconfiguration 2022-01-26 18:36:09 +01:00
Jared Boone
46fd11af5b Si5351C: Extract best block source function into hackrf_core. 
It's not an Si5351C driver thing, but a HackRF thing. Also added a driver function to check if CLKIN signal is valid, and made use of it, instead of opaque register read code.
 2019-03-20 11:16:44 -07:00
Jared Boone
d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO 
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
 2019-01-18 16:09:14 -08:00
Dominic Spill
3f569a8ad4 hackrf_clock: Allow CLKOUT to be enabled / disabled 
hackrf_clock -o 1 / hackrf_clock -o 0
 2017-11-07 11:23:48 -07:00
Dominic Spill
00b6099bb3 Make comments more informative (possibly) 2017-02-28 15:25:27 -07:00
Dominic Spill
0a48dccd66 CLOKOUT off by default 2017-02-21 18:38:50 -07:00
Dominic Spill
15ea074bdb Clean up Si5351c initialisation code 2017-02-21 17:43:19 -07:00
Dominic Spill
3eb00ed0df Disable CLK7 and power down CLK6/7 to reduce emissions 2017-02-20 12:34:35 -07:00
Dominic Spill
49257e60e3 Remove Jellybean support from firmware 
- nobody has a jellybean board
 2017-02-14 21:33:52 -07:00
schneider
c0c0fab368 chore(rad1o): White space fixes and cleanup 2017-02-03 19:27:19 +01:00
schneider
9d8890ae62 fix(rad1o): gpio cleanup 2017-01-27 21:42:48 +01:00
schneider
35ca538c18 Merge remote-tracking branch 'mossmann/master' into rad1o 
Just a very rough merge to get off the ground. Major parts are not yet
implemented. The mixer intergration is in a messed up state. Part which
need work have been marked with XXX

Conflicts:
	firmware/common/hackrf_core.c
	firmware/common/hackrf_core.h
	firmware/common/max2837.c
	firmware/common/max2837.h
	firmware/common/rf_path.c
	firmware/common/rffc5071.c
	firmware/common/rffc5071.h
	firmware/common/sgpio.c
	firmware/common/si5351c.c
	firmware/common/tuning.c
	firmware/common/w25q80bv.c
	firmware/common/w25q80bv.h
	firmware/common/xapp058/ports.c
	firmware/hackrf-common.cmake
	firmware/hackrf_usb/hackrf_usb.c
	firmware/hackrf_usb/usb_api_register.c
	firmware/hackrf_usb/usb_api_transceiver.c
	host/hackrf-tools/src/hackrf_transfer.c
 2017-01-26 00:21:58 +01:00
Tobias Schneider
9e827b56be hack(rad1o): Lower noise configuration 2015-12-05 23:46:59 +01:00
Tobias Schneider
c79c53c52f chore(name): We are now rad1o 2015-06-07 23:33:24 +02:00
Tobias Schneider
c05929fe25 fix(common, hackf_usb): Make it compile for rad10 2015-06-06 18:49:09 +02:00
Jared Boone
28d629e099 Si5351C: Bring I2C wrapper into main driver. 2014-11-12 18:32:00 -08:00
Jared Boone
3bc41f1480 Si5351C: Un-singleton the high- and low-level drivers. Proper. 2014-11-10 16:27:35 -08:00
Jared Boone
0bf84d974e Si5351C: Extract low-level driver code. 2014-11-10 16:27:09 -08:00
Michael Ossmann
69c4997727 fixed bug #130, CLKIN failure 2014-08-28 11:34:30 -06:00
Michael Ossmann
15bda174c7 maintain PLLA on XTAL and PLLB on CLKIN at all times (makes automatic clock source switching more reliable) 2014-03-14 22:27:30 -06:00
Michael Ossmann
ca04d7c04b activated CLKOUT (always on) and CLKIN (automatically used when detected) 2014-03-14 21:28:13 -06:00
Jared Boone
fb5dc6d5e0 Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/si5351c.c

Preferred Si5351C configuration that drives 40MHz into the LPC43xx GP_CLKIN.
Added HACKRF_ONE qualifier for CPLD TMS/TDI swap.
 2014-01-07 16:48:52 -08:00
Jared Boone
7f35ceaff2 Set Si5351C CLK7 output to drive LPC GP_CLKIN at 40MHz, so that activity (e.g. audio) on the LPC can be synchronized with the baseband sample rate. 2013-12-31 20:09:44 -08:00
Michael Ossmann
6b482b94da set crystal load capacitance to 8 pF 2013-12-12 15:47:00 -07:00
Michael Ossmann
99803c26cb another clock strength adjustment 2013-11-22 17:50:10 -07:00
Michael Ossmann
ebaccf46f4 adjusted clock generator output drive strength 2013-11-22 17:24:53 -07:00
Jared Boone
b285b91e4c Merge remote-tracking branch 'mossmann/master' into jboone_refactor_20130906 
Conflicts:
	firmware/common/hackrf_core.h
	firmware/common/rffc5071.c
 2013-11-20 18:43:40 -08:00
Michael Ossmann
5b14636c2c initial firmware support for HackRF One 2013-11-19 10:01:26 -07:00
Jared Boone
06da7fd83a Reduce drive strength from clock generator (Si5351C) to first mixer (RFFC5072). This reduces every-50MHz spurs in RX by 10 to 15dB. 2013-09-22 11:54:37 -07:00
Hoernchen
1e326997ed firmware: enable int mode if div is even integer 
to improve jitter performance
 2013-06-07 23:10:35 +02:00
Hoernchen
1925649a01 firmware: fractional sample rates 2013-06-07 14:29:14 +02:00
Hoernchen
a95f49b543 disable si clock to lpc 
leaving it on but unused causes major spurs to appear all over the
place..
 2013-06-05 17:35:01 +02:00
Hoernchen
7f6a730c6e si clock for the lpc 2013-05-29 17:12:06 +02:00
Jared Boone
4f9a5a1ba4 Fix-ups to copyrights -- missing e-mail address and inconsistent formatting. 2012-10-06 19:14:55 -07:00
Michael Ossmann
2c813ec41e Jawbreaker clock generator configuration 2012-09-19 13:43:16 -06:00
Michael Ossmann
cbd2d98c7d fixed bad output spectrum. problem was P3 = 0 in si5351c pll, similar to commit b595de647077f208c534e4efc0bce92f25378fb8 2012-08-22 10:41:53 -06:00
Jared Boone
9a53fd3a07 New CPLD .svf. 
Change Si5351C CLK2 to 10MHz.
Keep CLK3 at 20MHz, but not inverted.
Source SGPIO8 from P1_12 instead of P9_6. (See "SGPIO Clock Routing") modification at https://github.com/mossmann/hackrf/wiki/Future-Hardware-Modifications ).
 2012-06-15 16:12:35 -07:00
Michael Ossmann
ad080a355a pull request #10, resolved conflicts 2012-06-13 21:21:34 -06:00
Jared Boone
02f61f4d64 Added r_div argument to si5351c_configure_multisynth(). Modified Jellybean clock setup to provide 10MHz clock to MAX5864 and 20MHz to CPLD (both inverted and non-inverted). 2012-06-13 17:53:10 -07:00
Michael Ossmann
056ddd0601 r divider configurable, added CLK5 for mixer reference input 2012-06-13 16:02:40 -06:00