36 Commits

Author SHA1 Message Date
Michael Ossmann
bdb6000bb4 h1r9: fix inverted spectrum on TX
Unify and clean up the firmware spectrum inversion handling for all
hardware platforms.
2023-01-06 14:33:56 +00:00
Michael Ossmann
51bae663fc h1r9: update pin assignments for board spin B 2023-01-06 14:33:53 +00:00
Michael Ossmann
7b5d8da821 h1r9: swap RX Q inversion 2023-01-06 14:33:53 +00:00
Michael Ossmann
06b9d7bee0 Clean up source code copyright notices. 2022-09-23 14:46:52 -04:00
Martin Ling
c3fdf402d7 Reformat all code to new clang-format standard. 2022-08-03 23:46:44 +01:00
Martin Ling
6cd9ca9483 sgpio: Clean up comments. 2022-08-03 23:03:15 +01:00
Martin Ling
51b76d33a6 sgpio: Remove a redundant variable. 2022-08-03 23:03:15 +01:00
Schuyler St. Leger
9ee25ab48a operacake: add support for port switching using SCTimer
Based on Schuyler St. Leger's operacake-sctimer branch
2021-10-14 14:36:18 +01:00
Jared Boone
d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).
2019-01-18 16:09:14 -08:00
Marco Bartolucci
533f9ee332 Hardware (CPLD-based) synchronisation
=======================================

This commit allows to synchronise multiple HackRFs with a synchronisation error **below 1 sampling period**

> WARNING: Use this at your own risk. If you don't know what you are doing you may damage your HackRF.
> The author takes no responsability for potential damages

Usage example: synchronise two HackRFs
======================================
1. Chose the master HackRF which will send the synchronisation pulse (HackRF0). HackRF1 will represent the slave hackrf.
2. Retreive the serial number of both HackRFs using `hackrf_info`
3. Use a wire to connect `SYNC_CMD` of HackRF0 to `SYNC_IN` of HackRF0 and HackRF1
4. Run `hackrf_transfer` with the argument `-H 1` to enable hardware synchronisation:
    ```
    $ hackrf_tranfer ... -r rec1.bin -d HackRF1_serial -H 1 | hackrf_transfer ... -r rec0.bin -d HackRF0_serial -H 1
    ```
rec0.bin and rec1.bin will have a time offset below 1 sampling period.
The 1PPS output of GNSS receivers can be used to synchronise HackRFs even if they are far from each other.
>DON'T APPLY INCOMPATIBLE VOLTAGE LEVELS TO THE CPLD PINS

Signal | Header |Pin | Description
-------|--------|----|------------
`SYNC_IN` | P28 | 16 | Synchronisation pulse input
`SYNC_CMD` | P28 | 15 | Synchronisation pulse output

Note:
=====
I had to remove CPLD-based decimation to use a GPIO for enabling hardware.

More info:
==========
[M. Bartolucci, J. A. Del Peral-Rosado, R. Estatuet-Castillo, J. A. Garcia-Molina, M. Crisci and G. E. Corazza, "Synchronisation of low-cost open source SDRs for navigation applications," 2016 8th ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing (NAVITEC), Noordwijk, 2016, pp. 1-7.](http://ieeexplore.ieee.org/document/7849328/)

[Alternative link](http://spcomnav.uab.es/docs/conferences/Bartolucci_NAVITEC_2016.pdf)
2017-05-16 11:39:44 +02:00
schneider
c0c0fab368 chore(rad1o): White space fixes and cleanup 2017-02-03 19:27:19 +01:00
schneider
f063f87c49 fix(sgpio): Update rad1o update_q_invert gpio access 2017-01-27 20:51:44 +01:00
schneider
35ca538c18 Merge remote-tracking branch 'mossmann/master' into rad1o
Just a very rough merge to get off the ground. Major parts are not yet
implemented. The mixer intergration is in a messed up state. Part which
need work have been marked with XXX

Conflicts:
	firmware/common/hackrf_core.c
	firmware/common/hackrf_core.h
	firmware/common/max2837.c
	firmware/common/max2837.h
	firmware/common/rf_path.c
	firmware/common/rffc5071.c
	firmware/common/rffc5071.h
	firmware/common/sgpio.c
	firmware/common/si5351c.c
	firmware/common/tuning.c
	firmware/common/w25q80bv.c
	firmware/common/w25q80bv.h
	firmware/common/xapp058/ports.c
	firmware/hackrf-common.cmake
	firmware/hackrf_usb/hackrf_usb.c
	firmware/hackrf_usb/usb_api_register.c
	firmware/hackrf_usb/usb_api_transceiver.c
	host/hackrf-tools/src/hackrf_transfer.c
2017-01-26 00:21:58 +01:00
Tobias Schneider
60b3ef3112 fix(sgpio): Fix rad1o HW bug which inverts RX Q
As it is only inverted in the RX path (in respect to the HackRF) we need
to distinguish between RX/TX and inverted and not inverted.
2015-07-27 11:30:52 +02:00
Jared Boone
5363ec3672 Use new GPIO API to abstract GPIO in various drivers.
Had to do it all at once due to name conflicts with API exposed in libopencm3.
Quite invasive patch! Also precipitated an LED API...
2014-11-15 16:26:59 -08:00
Jared Boone
422173a5f7 SGPIO: Add CPLD RX Q channel inversion, API to control. 2014-08-11 13:02:02 -07:00
Jared Boone
0ab6a92ae6 Change SGPIO CPLD decimation API interface to be one-based (decimation of 1 to 8). 2014-08-11 13:01:50 -07:00
Jared Boone
c6b1ec2979 Adjust SGPIO GPDMA trigger slice data to a single clock width pulse. Previously, it was 3 clocks long with a 4 clock period, which *seemed* to address GPDMA data drop-outs at maximum baseband speed (20Msps complex). 2013-12-31 20:27:14 -08:00
Jared Boone
2fab6c40cd Extract SGPIO multi_slice configuration argument into an init-time function, so it doesn't need to be passed each time the SGPIO interface direction is changed. 2013-12-08 12:21:41 -08:00
Jared Boone
50ec268794 Bracket SGPIO GPDMA slice configuration with multislice==false test. It only makes sense in single slice mode (until I have a clever idea for doing GPDMA with multiple slices). 2013-12-08 12:14:00 -08:00
Jared Boone
809df425c1 Add SGPIO configuration to support GPDMA interrupts. 2013-12-08 11:54:50 -08:00
Jared Boone
91a7ca4983 Fix return value on SGPIO decimation function. 2013-11-20 15:08:59 -08:00
Jared Boone
e3f9e204c1 Relocate SGPIO pin configuration -- it only needs to be done once. 2013-11-20 13:22:19 -08:00
Jared Boone
3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.
2013-11-19 19:52:06 -08:00
Jared Boone
967e699815 Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values. 2013-11-17 22:23:08 -08:00
Jared Boone
2e2275ed51 Pull out leaky tri-state transceiver_mode value from sgpio_configure(), replace with SGPIO_DIRECTION_* #defines. 2013-09-17 22:29:41 -07:00
Jared Boone
52dda32a18 Adjust logic in sgpio_configure() to treat transceiver modes outside TX and RX as RX. "OFF", for example... 2013-09-17 15:32:11 -07:00
TitanMKD
b8590db02a Comment fix. 2013-04-04 19:48:28 +02:00
TitanMKD
118953b451 Lot of comments added. 2013-04-04 19:19:59 +02:00
Jared Boone
cc5f1c61c7 Fix clock edge for TX mode. TX data was completely crapped up due to skew on my Jellybean/Lemondrop board. Hopefully, this also applies to Jawbreaker. I'll recheck once I have hardware in-hand. 2012-11-02 22:34:43 -07:00
Jared Boone
9824a723b7 Moved invariant in sgpio_configure() loop out of loop. Originally, so I could use the value to calculate another invariant. 2012-10-12 09:45:18 -07:00
Jared Boone
a1af4356b6 Reworked sgpio.c to make use of #defines for fields, instead of hard-coding shifts. Proper. 2012-10-11 20:46:21 -07:00
Jared Boone
9b579232a7 Consolidated single-slice SGPIO configuration functions into single sgpio_configure() function. 2012-10-11 15:45:28 -07:00
Jared Boone
1bad2d8536 Consolidated two "deep" SGPIO configuration functions into one, qualified by transceiver mode (RX or TX). 95-ish % of the code was common. 2012-10-11 15:18:16 -07:00
Jared Boone
8291d7fac0 Add SGPIO configuration function for "deep" (8-slice) TX mode. 2012-10-11 13:04:30 -07:00
Jared Boone
5989465eb9 Add SGPIO configuration API and code, extracted from existing SGPIO projects. 2012-10-10 14:30:28 -07:00