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CPLD: Pull up HOST_SYNC signal, which is usually floating.

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HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady.

In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.
This commit is contained in:
Jared Boone
2019-01-16 17:55:45 -08:00
parent 454e32b8c8
commit f8b6e9145c
2 changed files with 3 additions and 3 deletions
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4
firmware/cpld/sgpio_if/sgpio_if.xise
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@ -91,7 +91,7 @@
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
@ -180,7 +180,7 @@
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Pullup" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>

2
firmware/cpld/sgpio_if/top.ucf
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@ -62,7 +62,7 @@ NET "HOST_DIRECTION" LOC = "P71" | IOSTANDARD = LVCMOS33 ;
NET "HOST_DISABLE" LOC = "P76" | IOSTANDARD = LVCMOS33 ;
NET "HOST_Q_INVERT" LOC = "P70" | IOSTANDARD = LVCMOS33 ;
NET "HOST_SYNC_EN" LOC = "P90" | IOSTANDARD = LVCMOS33 ;
NET "HOST_SYNC" LOC = "P55" | IOSTANDARD = LVCMOS33;
NET "HOST_SYNC" LOC = "P55" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "HOST_SYNC_CMD" LOC = "P56" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
#PACE: Start of PACE Area Constraints