diff --git a/firmware/cpld/sgpio_if/sgpio_if.xise b/firmware/cpld/sgpio_if/sgpio_if.xise
index 0ac6ecc6..4a238dc8 100755
--- a/firmware/cpld/sgpio_if/sgpio_if.xise
+++ b/firmware/cpld/sgpio_if/sgpio_if.xise
@@ -91,7 +91,7 @@
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
@@ -180,7 +180,7 @@
     <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Pullup" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/firmware/cpld/sgpio_if/top.ucf b/firmware/cpld/sgpio_if/top.ucf
index 82aaca90..58d77277 100755
--- a/firmware/cpld/sgpio_if/top.ucf
+++ b/firmware/cpld/sgpio_if/top.ucf
@@ -62,7 +62,7 @@ NET "HOST_DIRECTION"  LOC = "P71" | IOSTANDARD = LVCMOS33 ;
 NET "HOST_DISABLE"  LOC = "P76" | IOSTANDARD = LVCMOS33 ; 
 NET "HOST_Q_INVERT"  LOC = "P70" | IOSTANDARD = LVCMOS33 ;
 NET "HOST_SYNC_EN" LOC = "P90" | IOSTANDARD = LVCMOS33 ; 
-NET "HOST_SYNC"  LOC = "P55" | IOSTANDARD = LVCMOS33; 
+NET "HOST_SYNC"  LOC = "P55" | IOSTANDARD = LVCMOS33 | PULLUP ; 
 NET "HOST_SYNC_CMD"  LOC = "P56" | IOSTANDARD = LVCMOS33  | SLEW = SLOW ; 
 
 #PACE: Start of PACE Area Constraints