Merge pull request #3 from TitanMKD/master
Example Blinky SPIFI to SRAM and some documentation
This commit is contained in:
Michael Ossmann
14
firmware/blinky_SPIFI_SRAM/Makefile
Normal file
14
firmware/blinky_SPIFI_SRAM/Makefile
Normal file
@ -0,0 +1,14 @@
|
||||
# Hey Emacs, this is a -*- makefile -*-
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||||
|
||||
# Target file name (without extension).
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||||
TARGET = blinky
|
||||
|
||||
# List C source files here. (C dependencies are automatically generated.)
|
||||
SRC = $(TARGET).c \
|
||||
$(LIBS_PATH)/LPC43xx_M4_Startup_ROM_to_RAM.c \
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$(LIBS_PATH)/LPC43xx_M4_Interrupts.c \
|
||||
$(LIBS_PATH)/hackrf_core.c
|
||||
|
||||
# Override Linker Script
|
||||
LINKER_SCRIPT = LPC4330_M4_ROM_to_RAM.ld
|
||||
include ../common/Makefile_inc.mk
|
||||
3
firmware/blinky_SPIFI_SRAM/README
Normal file
3
firmware/blinky_SPIFI_SRAM/README
Normal file
@ -0,0 +1,3 @@
|
||||
This is the simplest example firmware for HackRF. It flashes three LEDs.
|
||||
This Example Start execution in SPIFI(ROM) and at startup, code from ROM is copied to RAM and shadow pointer is modified to RAM.
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So at end all the code and vector table is executed from RAM.
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||||
57
firmware/blinky_SPIFI_SRAM/blinky.c
Normal file
57
firmware/blinky_SPIFI_SRAM/blinky.c
Normal file
@ -0,0 +1,57 @@
|
||||
/*
|
||||
* Copyright 2010 - 2012 Michael Ossmann
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||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include "hackrf_core.h"
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||||
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||||
void wait(uint8_t duration)
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{
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volatile uint32_t i;
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for (i = 0; i < duration * 1000000; i++);
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}
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|
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uint32_t boot0, boot1, boot2, boot3;
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int main()
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{
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gpio_init();
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||||
|
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EN1V8_SET;
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EN1V8_CLR;
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||||
|
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while (1) {
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boot0 = BOOT0;
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boot1 = BOOT1;
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boot2 = BOOT2;
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boot3 = BOOT3;
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LED1_SET;
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LED2_SET;
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LED3_SET;
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wait(1);
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LED1_CLR;
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LED2_CLR;
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LED3_CLR;
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wait(1);
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}
|
||||
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return 0 ;
|
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}
|
||||
163
firmware/common/LPC4330_M4_ROM_to_RAM.ld
Normal file
163
firmware/common/LPC4330_M4_ROM_to_RAM.ld
Normal file
@ -0,0 +1,163 @@
|
||||
/*
|
||||
* Copyright 2010 - 2012 Michael Ossmann
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* Copyright 2012 Benjamin Vernoux
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*
|
||||
* This file is part of HackRF
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
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||||
*/
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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ENTRY(_start)
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SEARCH_DIR(.)
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GROUP(libgcc.a libc.a libm.a libnosys.a)
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|
||||
MEMORY
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{
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/*
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||||
* Our code is installed in SPIFI(ROM) at 0x80000000 it is addressed through the 256M shadow area at 0x00000000 at Boot.
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* Reset_Handler call Reset_Handler_ROM_to_RAM(executed in SPIFI) and Copy the code from ROM to RAM,
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* and set shadow pointer to RAM, then the code execution continue in RAM.
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*/
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rom (rx) : ORIGIN = 0x80000000, LENGTH = 128K /* Real ROM Address It cannot exceed RAM size (Real Size is 1MB) */
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ram (rwx) : ORIGIN = 0x10000000, LENGTH = 128K /* Real RAM Address */
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||||
shadow_ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128K /* 128 Kb Real Address is 0x10000000 but remapped to Shadow 0x00000000 */
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/* there are some additional RAM regions */
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}
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|
||||
/*
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* much copied from: Linker script for Cortex-M3
|
||||
*
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||||
* Version:CodeSourcery Sourcery G++ Lite 2007q3-53
|
||||
* BugURL:https://support.codesourcery.com/GNUToolchain/
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||||
*
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||||
* Copyright 2007 CodeSourcery.
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*
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||||
* The authors hereby grant permission to use, copy, modify, distribute,
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||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
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* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
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*/
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EXTERN(Reset_Handler)
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ENTRY(Reset_Handler)
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SECTIONS
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{
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.text :
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{
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_text_ram = . + ORIGIN(ram); /* Start of Code in RAM */
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. = ALIGN(0x400); /* Ensure that vector table is aligned as hardware requires. */
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_interrupt_vector_table = .;
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KEEP(*(.irq_handler_table))
|
||||
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
|
||||
. = ALIGN(4);
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||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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|
||||
. = ALIGN(4);
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||||
__init_array_start = .;
|
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
|
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__init_array_end = .;
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||||
|
||||
. = ALIGN(0x4);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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||||
|
||||
KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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||||
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. = ALIGN(8);
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_etext = .;
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} > shadow_ram
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.ARM.extab :
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{
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||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
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||||
} > shadow_ram
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||||
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||||
__exidx_start = .;
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||||
.ARM.exidx :
|
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{
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||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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||||
} > shadow_ram
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__exidx_end = .;
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_etext = .;
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_etext_ram = . + ORIGIN(ram);
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_etext_rom = . + ORIGIN(rom);
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.data :
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{
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_data = .;
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*(vtable)
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*(.data*)
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_edata = .;
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} > shadow_ram
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/* zero initialized data */
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.bss :
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{
|
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_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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_ebss = .;
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__bss_end__ = .;
|
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} > shadow_ram
|
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|
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/* Where we put the heap with cr_clib */
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.cr_heap :
|
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{
|
||||
end = .;
|
||||
__end__ = .;
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_pvHeapStart = .;
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} > shadow_ram
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/* Leave room above stack for IAP to run */
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_StackTop = ORIGIN(ram) + (ORIGIN(shadow_ram) + LENGTH(shadow_ram) - 32);
|
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|
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}
|
||||
118
firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c
Normal file
118
firmware/common/LPC43xx_M4_Startup_ROM_to_RAM.c
Normal file
@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright 2012 Benjamin Vernoux
|
||||
*
|
||||
* This file is part of HackRF.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
/*
|
||||
Copyright 2010-07 By Opendous Inc. (www.MicropendousX.org)
|
||||
NVIC handler info copied from NXP User Manual UM10360
|
||||
|
||||
Start-up code for LPC17xx. See TODOs for
|
||||
modification instructions.
|
||||
|
||||
Permission to use, copy, modify, and distribute this software
|
||||
and its documentation for any purpose and without fee is hereby
|
||||
granted, provided that the above copyright notice appear in all
|
||||
copies and that both that the copyright notice and this
|
||||
permission notice and warranty disclaimer appear in supporting
|
||||
documentation, and that the name of the author not be used in
|
||||
advertising or publicity pertaining to distribution of the
|
||||
software without specific, written prior permission.
|
||||
|
||||
The author disclaim all warranties with regard to this
|
||||
software, including all implied warranties of merchantability
|
||||
and fitness. In no event shall the author be liable for any
|
||||
special, indirect or consequential damages or any damages
|
||||
whatsoever resulting from loss of use, data or profits, whether
|
||||
in an action of contract, negligence or other tortious action,
|
||||
arising out of or in connection with the use or performance of
|
||||
this software.
|
||||
*/
|
||||
|
||||
#include <lpc43.h>
|
||||
|
||||
#define CREG_BASE 0x40043000
|
||||
#define MMIO32(addr) (*(volatile unsigned long *)(addr))
|
||||
#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
|
||||
|
||||
/* Reset_Handler_ROM_to_RAM variables defined in linker script */
|
||||
extern unsigned long _text_ram; /* Correspond to start of Code in RAM */
|
||||
extern unsigned long _etext_ram; /* Correspond to end of Code in RAM */
|
||||
extern unsigned long _etext_rom; /* Correspond to end of Code in ROM */
|
||||
|
||||
|
||||
/* Reset_Handler variables defined in linker script */
|
||||
extern unsigned long _interrupt_vector_table;
|
||||
extern unsigned long _data;
|
||||
extern unsigned long _edata;
|
||||
extern unsigned long _etext;
|
||||
extern unsigned long _bss;
|
||||
extern unsigned long _ebss;
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern int main(void);
|
||||
|
||||
/* Code to be Copied from ROM to RAM */
|
||||
void Reset_Handler_ROM_to_RAM(void)
|
||||
{
|
||||
unsigned long *src, *dest;
|
||||
|
||||
// Copy the code from ROM to Real RAM
|
||||
src = &_etext_rom-(&_etext_ram-&_text_ram);
|
||||
for(dest = &_text_ram; dest < &_etext_ram; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Change Shadow memory to Real RAM */
|
||||
CREG_M4MEMMAP = &_text_ram;
|
||||
|
||||
/* Continue Execution in RAM */
|
||||
}
|
||||
|
||||
/* Reset Handler */
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
unsigned long *src, *dest;
|
||||
|
||||
Reset_Handler_ROM_to_RAM();
|
||||
|
||||
// Copy the data segment initializers from flash to SRAM
|
||||
src = &_etext;
|
||||
for(dest = &_data; dest < &_edata; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
// Initialize the .bss segment of memory to zeros
|
||||
src = &_bss;
|
||||
while (src < &_ebss)
|
||||
{
|
||||
*src++ = 0;
|
||||
}
|
||||
|
||||
__libc_init_array();
|
||||
|
||||
// Set the vector table location.
|
||||
SCB_VTOR = &_interrupt_vector_table;
|
||||
|
||||
main();
|
||||
|
||||
// In case main() fails, have something to breakpoint
|
||||
while (1) {;}
|
||||
}
|
||||
152
hardware/jellybean/JellyBean_PinMux.pmx
Normal file
152
hardware/jellybean/JellyBean_PinMux.pmx
Normal file
@ -0,0 +1,152 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<PinMuxDesign>
|
||||
<Chip>LPC4330FBD144</Chip>
|
||||
<Peripheral Name="ADC0">
|
||||
<Signals BallNumber="5" Signal="ADC0_0"/>
|
||||
<Signals BallNumber="142" Signal="ADC0_2"/>
|
||||
<Signals BallNumber="143" Signal="ADC0_5"/>
|
||||
<Signals BallNumber="141" Signal="ADC0_6"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="GPIO0">
|
||||
<Signals BallNumber="95" Signal="GPIO0[7]"/>
|
||||
<Signals BallNumber="41" Signal="GPIO0[8]"/>
|
||||
<Signals BallNumber="42" Signal="GPIO0[9]"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="GPIO1">
|
||||
<Signals BallNumber="101" Signal="GPIO1[10]"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="GPIO2">
|
||||
<Signals BallNumber="0" Signal="GPIO2[0]"/>
|
||||
<Signals BallNumber="2" Signal="GPIO2[1]"/>
|
||||
<Signals BallNumber="7" Signal="GPIO2[2]"/>
|
||||
<Signals BallNumber="8" Signal="GPIO2[4]"/>
|
||||
<Signals BallNumber="9" Signal="GPIO2[5]"/>
|
||||
<Signals BallNumber="10" Signal="GPIO2[6]"/>
|
||||
<Signals BallNumber="102" Signal="GPIO2[8]"/>
|
||||
<Signals BallNumber="36" Signal="GPIO2[9]"/>
|
||||
<Signals BallNumber="38" Signal="GPIO2[10]"/>
|
||||
<Signals BallNumber="45" Signal="GPIO2[11]"/>
|
||||
<Signals BallNumber="53" Signal="GPIO2[12]"/>
|
||||
<Signals BallNumber="56" Signal="GPIO2[13]"/>
|
||||
<Signals BallNumber="57" Signal="GPIO2[14]"/>
|
||||
<Signals BallNumber="62" Signal="GPIO2[15]"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="GPIO3">
|
||||
<Signals BallNumber="73" Signal="GPIO3[0]"/>
|
||||
<Signals BallNumber="77" Signal="GPIO3[1]"/>
|
||||
<Signals BallNumber="81" Signal="GPIO3[4]"/>
|
||||
<Signals BallNumber="96" Signal="GPIO3[5]"/>
|
||||
<Signals BallNumber="99" Signal="GPIO3[6]"/>
|
||||
<Signals BallNumber="100" Signal="GPIO3[7]"/>
|
||||
<Signals BallNumber="112" Signal="GPIO3[9]"/>
|
||||
<Signals BallNumber="114" Signal="GPIO3[10]"/>
|
||||
<Signals BallNumber="116" Signal="GPIO3[11]"/>
|
||||
<Signals BallNumber="131" Signal="GPIO3[12]"/>
|
||||
<Signals BallNumber="132" Signal="GPIO3[13]"/>
|
||||
<Signals BallNumber="133" Signal="GPIO3[14]"/>
|
||||
<Signals BallNumber="139" Signal="GPIO3[15]"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="GPIO5">
|
||||
<Signals BallNumber="94" Signal="GPIO5[6]"/>
|
||||
<Signals BallNumber="97" Signal="GPIO5[7]"/>
|
||||
<Signals BallNumber="68" Signal="GPIO5[18]"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="I2C0">
|
||||
<Signals BallNumber="91" Signal="I2C0_SCL"/>
|
||||
<Signals BallNumber="92" Signal="I2C0_SDA"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="I2S0">
|
||||
<Signals BallNumber="98" Signal="I2S0_TX_MCLK"/>
|
||||
<Signals BallNumber="111" Signal="I2S0_TX_SCK"/>
|
||||
<Signals BallNumber="115" Signal="I2S0_TX_SDA"/>
|
||||
<Signals BallNumber="113" Signal="I2S0_TX_WS"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="JTAG">
|
||||
<Signals BallNumber="27" Signal="DBGEN"/>
|
||||
<Signals BallNumber="26" Signal="TCK/SWDCLK"/>
|
||||
<Signals BallNumber="25" Signal="TDI "/>
|
||||
<Signals BallNumber="30" Signal="TDO/SWO"/>
|
||||
<Signals BallNumber="29" Signal="TMS/SWDIO"/>
|
||||
<Signals BallNumber="28" Signal="TRST"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="RTC">
|
||||
<Signals BallNumber="126" Signal="VBAT"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="SCT">
|
||||
<Signals BallNumber="90" Signal="CTIN_2"/>
|
||||
<Signals BallNumber="107" Signal="CTIN_4"/>
|
||||
<Signals BallNumber="79" Signal="CTIN_6"/>
|
||||
<Signals BallNumber="103" Signal="CTOUT_2"/>
|
||||
<Signals BallNumber="105" Signal="CTOUT_4"/>
|
||||
<Signals BallNumber="104" Signal="CTOUT_5"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="SD/MMC">
|
||||
<Signals BallNumber="59" Signal="SD_CD"/>
|
||||
<Signals BallNumber="44" Signal="SD_CLK"/>
|
||||
<Signals BallNumber="48" Signal="SD_CMD"/>
|
||||
<Signals BallNumber="51" Signal="SD_DAT0"/>
|
||||
<Signals BallNumber="52" Signal="SD_DAT1"/>
|
||||
<Signals BallNumber="54" Signal="SD_DAT2"/>
|
||||
<Signals BallNumber="55" Signal="SD_DAT3"/>
|
||||
<Signals BallNumber="47" Signal="SD_POW"/>
|
||||
<Signals BallNumber="50" Signal="SD_VOLT0"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="SGPIO">
|
||||
<Signals BallNumber="31" Signal="SGPIO0"/>
|
||||
<Signals BallNumber="33" Signal="SGPIO1"/>
|
||||
<Signals BallNumber="61" Signal="SGPIO2"/>
|
||||
<Signals BallNumber="63" Signal="SGPIO3"/>
|
||||
<Signals BallNumber="78" Signal="SGPIO4"/>
|
||||
<Signals BallNumber="82" Signal="SGPIO5"/>
|
||||
<Signals BallNumber="83" Signal="SGPIO6"/>
|
||||
<Signals BallNumber="37" Signal="SGPIO7"/>
|
||||
<Signals BallNumber="71" Signal="SGPIO8"/>
|
||||
<Signals BallNumber="6" Signal="SGPIO9"/>
|
||||
<Signals BallNumber="60" Signal="SGPIO10"/>
|
||||
<Signals BallNumber="65" Signal="SGPIO11"/>
|
||||
<Signals BallNumber="66" Signal="SGPIO12"/>
|
||||
<Signals BallNumber="14" Signal="SGPIO13"/>
|
||||
<Signals BallNumber="32" Signal="SGPIO14"/>
|
||||
<Signals BallNumber="34" Signal="SGPIO15"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="SPIFI">
|
||||
<Signals BallNumber="123" Signal="SPIFI_CS"/>
|
||||
<Signals BallNumber="121" Signal="SPIFI_MISO"/>
|
||||
<Signals BallNumber="122" Signal="SPIFI_MOSI"/>
|
||||
<Signals BallNumber="117" Signal="SPIFI_SCK"/>
|
||||
<Signals BallNumber="120" Signal="SPIFI_SIO2"/>
|
||||
<Signals BallNumber="118" Signal="SPIFI_SIO3"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="SSP1">
|
||||
<Signals BallNumber="43" Signal="SSP1_MISO"/>
|
||||
<Signals BallNumber="46" Signal="SSP1_MOSI"/>
|
||||
<Signals BallNumber="67" Signal="SSP1_SCK"/>
|
||||
<Signals BallNumber="69" Signal="SSP1_SSEL"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="TRACE">
|
||||
<Signals BallNumber="119" Signal="TRACECLK"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="UART0">
|
||||
<Signals BallNumber="80" Signal="U0_RXD"/>
|
||||
<Signals BallNumber="74" Signal="U0_TXD"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="UART3">
|
||||
<Signals BallNumber="87" Signal="U3_RXD"/>
|
||||
<Signals BallNumber="86" Signal="U3_TXD"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="USB0">
|
||||
<Signals BallNumber="19" Signal="USB0_DM"/>
|
||||
<Signals BallNumber="17" Signal="USB0_DP"/>
|
||||
<Signals BallNumber="85" Signal="USB0_IND0"/>
|
||||
<Signals BallNumber="84" Signal="USB0_IND1"/>
|
||||
<Signals BallNumber="23" Signal="USB0_RREF"/>
|
||||
<Signals BallNumber="20" Signal="USB0_VBUS"/>
|
||||
<Signals BallNumber="16" Signal="USB0_VDDA3V3"/>
|
||||
<Signals BallNumber="15" Signal="USB0_VDDA3V3_DRIVER"/>
|
||||
<Signals BallNumber="22" Signal="USB0_VSSA_REF"/>
|
||||
<Signals BallNumber="18" Signal="USB0_VSSA_TERM"/>
|
||||
</Peripheral>
|
||||
<Peripheral Name="WAKEUP">
|
||||
<Signals BallNumber="129" Signal="WAKEUP0"/>
|
||||
</Peripheral>
|
||||
</PinMuxDesign>
|
||||
BIN
hardware/jellybean/JellyBean_TPS62410.ods
Normal file
BIN
hardware/jellybean/JellyBean_TPS62410.ods
Normal file
Binary file not shown.
Binary file not shown.
Reference in New Issue
Block a user