Merge branch 'master' of https://github.com/mossmann/hackrf
Conflicts: firmware/common/hackrf_core.c
This commit is contained in:
Jared Boone
@ -28,8 +28,6 @@
|
||||
#include <libopencm3/lpc43xx/scu.h>
|
||||
#include <libopencm3/lpc43xx/ssp.h>
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
|
||||
void delay(uint32_t duration)
|
||||
{
|
||||
uint32_t i;
|
||||
@ -51,6 +49,19 @@ void cpu_clock_init(void)
|
||||
si5351c_configure_pll_sources_for_xtal();
|
||||
si5351c_configure_pll1_multisynth();
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
/*
|
||||
* Jellybean/Lemondrop clocks:
|
||||
* CLK0 -> MAX2837
|
||||
* CLK1 -> MAX5864/CPLD
|
||||
* CLK2 -> CPLD
|
||||
* CLK3 -> CPLD
|
||||
* CLK4 -> LPC4330
|
||||
* CLK5 -> RFFC5072
|
||||
* CLK6 -> extra
|
||||
* CLK7 -> extra
|
||||
*/
|
||||
|
||||
/* MS0/CLK0 is the source for the MAX2837 clock input. */
|
||||
si5351c_configure_multisynth(0, 2048, 0, 1, 0); /* 40MHz */
|
||||
|
||||
@ -68,6 +79,42 @@ void cpu_clock_init(void)
|
||||
|
||||
/* MS5/CLK5 is the source for the RFFC5071 mixer. */
|
||||
si5351c_configure_multisynth(5, 1536, 0, 1, 0); /* 50MHz */
|
||||
#endif
|
||||
|
||||
#ifdef JAWBREAKER
|
||||
/*
|
||||
* Jawbreaker clocks:
|
||||
* CLK0 -> MAX5864/CPLD
|
||||
* CLK1 -> CPLD
|
||||
* CLK2 -> SGPIO
|
||||
* CLK3 -> external clock output
|
||||
* CLK4 -> RFFC5072
|
||||
* CLK5 -> MAX2837
|
||||
* CLK6 -> none
|
||||
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
|
||||
*/
|
||||
|
||||
/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
|
||||
si5351c_configure_multisynth(0, 4608, 0, 1, 1); /* 10MHz */
|
||||
|
||||
/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
|
||||
si5351c_configure_multisynth(1, 4608, 0, 1, 0); /* 20MHz */
|
||||
|
||||
/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
|
||||
si5351c_configure_multisynth(2, 4608, 0, 1, 0); /* 20MHz */
|
||||
|
||||
/* MS0/CLK3 is the source for the external clock output. */
|
||||
si5351c_configure_multisynth(3, 4608, 0, 1, 0); /* 20MHz */
|
||||
|
||||
/* MS4/CLK4 is the source for the RFFC5071 mixer. */
|
||||
si5351c_configure_multisynth(4, 1536, 0, 1, 0); /* 50MHz */
|
||||
|
||||
/* MS5/CLK5 is the source for the MAX2837 clock input. */
|
||||
si5351c_configure_multisynth(5, 2048, 0, 1, 0); /* 40MHz */
|
||||
|
||||
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
|
||||
//si5351c_configure_multisynth(7, 8021, 0, 3, 0); /* 12MHz */
|
||||
#endif
|
||||
|
||||
si5351c_configure_clock_control();
|
||||
si5351c_enable_clock_outputs();
|
||||
@ -75,14 +122,18 @@ void cpu_clock_init(void)
|
||||
//FIXME disable I2C
|
||||
|
||||
/*
|
||||
* 12MHz clock is entering LPC XTAL1/OSC input now.
|
||||
* 12MHz clock is entering LPC XTAL1/OSC input now. On
|
||||
* Jellybean/Lemondrop, this is a signal from the clock generator. On
|
||||
* Jawbreaker, there is a 12 MHz crystal at the LPC.
|
||||
* Set up PLL1 to run from XTAL1 input.
|
||||
*/
|
||||
|
||||
//FIXME a lot of the details here should be in a CGU driver
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
/* configure xtal oscillator for external clock input signal */
|
||||
CGU_XTAL_OSC_CTRL |= CGU_XTAL_OSC_CTRL_BYPASS;
|
||||
#endif
|
||||
|
||||
/* set xtal oscillator to low frequency mode */
|
||||
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
|
||||
@ -203,56 +254,3 @@ void ssp1_set_mode_max5864(void)
|
||||
SSP_MASTER,
|
||||
SSP_SLAVE_OUT_ENABLE);
|
||||
}
|
||||
|
||||
void pin_setup(void) {
|
||||
/* Release CPLD JTAG pins */
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
|
||||
|
||||
GPIO_DIR(PORT_CPLD_TDO) &= ~PIN_CPLD_TDO;
|
||||
GPIO_DIR(PORT_CPLD_TCK) &= ~PIN_CPLD_TCK;
|
||||
GPIO_DIR(PORT_CPLD_TMS) &= ~PIN_CPLD_TMS;
|
||||
GPIO_DIR(PORT_CPLD_TDI) &= ~PIN_CPLD_TDI;
|
||||
|
||||
/* Configure SCU Pin Mux as GPIO */
|
||||
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
|
||||
|
||||
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
|
||||
|
||||
/* Configure all GPIO as Input (safe state) */
|
||||
GPIO0_DIR = 0;
|
||||
GPIO1_DIR = 0;
|
||||
GPIO2_DIR = 0;
|
||||
GPIO3_DIR = 0;
|
||||
GPIO4_DIR = 0;
|
||||
GPIO5_DIR = 0;
|
||||
GPIO6_DIR = 0;
|
||||
GPIO7_DIR = 0;
|
||||
|
||||
/* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
|
||||
GPIO2_DIR |= (PIN_LED1 | PIN_LED2 | PIN_LED3);
|
||||
|
||||
/* GPIO3[6] on P6_10 as output. */
|
||||
GPIO3_DIR |= PIN_EN1V8;
|
||||
|
||||
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
|
||||
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
|
||||
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
|
||||
}
|
||||
|
||||
void enable_1v8_power(void) {
|
||||
gpio_set(PORT_EN1V8, PIN_EN1V8);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -32,15 +32,19 @@ extern "C"
|
||||
#include <stdint.h>
|
||||
|
||||
/* hardware identification number */
|
||||
#define BOARD_ID_JELLYBEAN 0
|
||||
#define BOARD_ID_JELLYBEAN 0
|
||||
#define BOARD_ID_JAWBREAKER 1
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
#define BOARD_ID BOARD_ID_JELLYBEAN
|
||||
#endif
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
#ifdef JAWBREAKER
|
||||
#define BOARD_ID BOARD_ID_JAWBREAKER
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Jellybean SCU PinMux
|
||||
* SCU PinMux
|
||||
*/
|
||||
|
||||
/* GPIO Output PinMux */
|
||||
@ -96,14 +100,28 @@ extern "C"
|
||||
#define SCU_AD_CS (P5_7) /* GPIO2[7] on P5_7 */
|
||||
|
||||
/* RFFC5071 GPIO serial interface PinMux */
|
||||
#ifdef JELLYBEAN
|
||||
#define SCU_MIXER_ENX (P7_0) /* GPIO3[8] on P7_0 */
|
||||
#define SCU_MIXER_SCLK (P7_1) /* GPIO3[9] on P7_1 */
|
||||
#define SCU_MIXER_SDATA (P7_2) /* GPIO3[10] on P7_2 */
|
||||
#define SCU_MIXER_RESETX (P7_3) /* GPIO3[11] on P7_3 */
|
||||
#endif
|
||||
#ifdef JAWBREAKER
|
||||
#define SCU_MIXER_ENX (P5_4) /* GPIO2[13] on P5_4 */
|
||||
#define SCU_MIXER_SCLK (P2_6) /* GPIO5[6] on P2_6 */
|
||||
#define SCU_MIXER_SDATA (P6_4) /* GPIO3[3] on P6_4 */
|
||||
#define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */
|
||||
#endif
|
||||
|
||||
/* RF LDO control */
|
||||
#ifdef JAWBREAKER
|
||||
#define RF_LDO_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
|
||||
#endif
|
||||
|
||||
/* TODO add other Pins */
|
||||
|
||||
/*
|
||||
* Jellybean GPIO Pins
|
||||
* GPIO Pins
|
||||
*/
|
||||
|
||||
/* GPIO Output */
|
||||
@ -125,10 +143,31 @@ extern "C"
|
||||
#define PIN_AD_CS (BIT7) /* GPIO2[7] on P5_7 */
|
||||
#define PORT_AD_CS (GPIO2) /* PORT for AD_CS */
|
||||
|
||||
#define PIN_MIXER_ENX (BIT8) /* GPIO3[8] on P7_0 */
|
||||
#define PIN_MIXER_SCLK (BIT9) /* GPIO3[9] on P7_1 */
|
||||
#define PIN_MIXER_SDATA (BIT10) /* GPIO3[10] on P7_2 */
|
||||
#define PORT_MIXER (GPIO3) /* PORT for mixer serial interface */
|
||||
#ifdef JELLYBEAN
|
||||
#define PIN_MIXER_ENX (BIT8) /* GPIO3[8] on P7_0 */
|
||||
#define PORT_MIXER_ENX (GPIO3)
|
||||
#define PIN_MIXER_SCLK (BIT9) /* GPIO3[9] on P7_1 */
|
||||
#define PORT_MIXER_SCLK (GPIO3)
|
||||
#define PIN_MIXER_SDATA (BIT10) /* GPIO3[10] on P7_2 */
|
||||
#define PORT_MIXER_SDATA (GPIO3)
|
||||
#define PIN_MIXER_RESETX (BIT11) /* GPIO3[11] on P7_3 */
|
||||
#define PORT_MIXER_RESETX (GPIO3)
|
||||
#endif
|
||||
#ifdef JAWBREAKER
|
||||
#define PIN_MIXER_ENX (BIT13) /* GPIO2[13] on P5_4 */
|
||||
#define PORT_MIXER_ENX (GPIO2)
|
||||
#define PIN_MIXER_SCLK (BIT6) /* GPIO5[6] on P2_6 */
|
||||
#define PORT_MIXER_SCLK (GPIO5)
|
||||
#define PIN_MIXER_SDATA (BIT3) /* GPIO3[3] on P6_4 */
|
||||
#define PORT_MIXER_SDATA (GPIO3)
|
||||
#define PIN_MIXER_RESETX (BIT14) /* GPIO2[14] on P5_5 */
|
||||
#define PORT_MIXER_RESETX (GPIO2)
|
||||
#endif
|
||||
|
||||
#ifdef JAWBREAKER
|
||||
#define PIN_RF_LDO_ENABLE (BIT9) /* GPIO2[9] on P5_0 */
|
||||
#define PORT_RF_LDO_ENABLE (GPIO2) /* PORT for RF_LDO_ENABLE */
|
||||
#endif
|
||||
|
||||
/* GPIO Input */
|
||||
#define PIN_BOOT0 (BIT8) /* GPIO0[8] on P1_1 */
|
||||
@ -147,14 +186,14 @@ extern "C"
|
||||
#define PORT_CPLD_TDI (GPIO3)
|
||||
|
||||
/* Read GPIO Pin */
|
||||
#define BOOT0_STATE ((GPIO0_PIN & PIN_BOOT0)==PIN_BOOT0)
|
||||
#define BOOT1_STATE ((GPIO0_PIN & PIN_BOOT1)==PIN_BOOT1)
|
||||
#define BOOT2_STATE ((GPIO5_PIN & PIN_BOOT2)==PIN_BOOT2)
|
||||
#define BOOT3_STATE ((GPIO1_PIN & PIN_BOOT3)==PIN_BOOT3)
|
||||
#define MIXER_SDATA_STATE ((GPIO3_PIN & PIN_MIXER_SDATA)==PIN_MIXER_SDATA)
|
||||
#define GPIO_STATE(port, pin) ((GPIO_PIN(port) & (pin)) == (pin))
|
||||
#define BOOT0_STATE GPIO_STATE(GPIO0, PIN_BOOT0)
|
||||
#define BOOT1_STATE GPIO_STATE(GPIO0, PIN_BOOT1)
|
||||
#define BOOT2_STATE GPIO_STATE(GPIO5, PIN_BOOT2)
|
||||
#define BOOT3_STATE GPIO_STATE(GPIO1, PIN_BOOT3)
|
||||
#define MIXER_SDATA_STATE GPIO_STATE(PORT_MIXER_SDATA, PIN_MIXER_SDATA)
|
||||
|
||||
/* TODO add other Pins */
|
||||
#endif
|
||||
|
||||
void delay(uint32_t duration);
|
||||
|
||||
|
||||
@ -24,6 +24,12 @@
|
||||
* program would do if it had a real spi library
|
||||
*/
|
||||
|
||||
/*
|
||||
* The actual part on Jawbreaker is the RFFC5072, not the RFFC5071, but the
|
||||
* RFFC5071 may be installed instead. The only difference between the parts is
|
||||
* that the RFFC5071 includes a second mixer.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "rffc5071.h"
|
||||
@ -103,13 +109,19 @@ void rffc5071_setup(void)
|
||||
scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_MIXER_SCLK, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_MIXER_SDATA, SCU_GPIO_FAST);
|
||||
scu_pinmux(SCU_MIXER_RESETX, SCU_GPIO_FAST);
|
||||
|
||||
/* Set GPIO pins as outputs. */
|
||||
GPIO3_DIR |= (PIN_MIXER_ENX | PIN_MIXER_SCLK | PIN_MIXER_SDATA);
|
||||
GPIO_DIR(PORT_MIXER_ENX) |= PIN_MIXER_ENX;
|
||||
GPIO_DIR(PORT_MIXER_SCLK) |= PIN_MIXER_SCLK;
|
||||
GPIO_DIR(PORT_MIXER_SDATA) |= PIN_MIXER_SDATA;
|
||||
GPIO_DIR(PORT_MIXER_RESETX) |= PIN_MIXER_RESETX;
|
||||
|
||||
/* set to known state */
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_ENX); /* active low */
|
||||
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
|
||||
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX); /* active low */
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
gpio_set(PORT_MIXER_RESETX, PIN_MIXER_RESETX); /* active low */
|
||||
#endif
|
||||
|
||||
/* initial setup */
|
||||
@ -133,24 +145,10 @@ void rffc5071_setup(void)
|
||||
* not control pins. */
|
||||
set_RFFC5071_SIPIN(1);
|
||||
|
||||
/* Initial settings for Lollipop switches, same for both
|
||||
* paths. These could use some #defines that iron out the
|
||||
* (non)inverted signals.
|
||||
*
|
||||
* bit0: SWTXB1 (!tx_bypass)
|
||||
* bit1: SWRXB1 (rx_bypass)
|
||||
* bit2: SWTXA1 (tx_hp)
|
||||
* bit3: unused (lock bit)
|
||||
* bit4: SWRXA1 (rx_hp)
|
||||
* bit5 SWD1 (!tx_ant)
|
||||
*
|
||||
* Unknown whether shift is needed. There are 7 register bits
|
||||
* to hold 6 GPO bits. */
|
||||
set_RFFC5071_P1GPO(0b010100<<1);
|
||||
set_RFFC5071_P2GPO(0b010100<<1);
|
||||
|
||||
/* send lock flag on GPO4 */
|
||||
set_RFFC5071_LOCK(1);
|
||||
#ifdef JAWBREAKER
|
||||
/* initial safe switch control settings */
|
||||
rffc5071_set_gpo(SWITCHCTRL_SAFE);
|
||||
#endif
|
||||
|
||||
/* GPOs are active at all times */
|
||||
set_RFFC5071_GATE(1);
|
||||
@ -185,69 +183,79 @@ uint16_t rffc5071_spi_read(uint8_t r) {
|
||||
return 0;
|
||||
#else
|
||||
/* make sure everything is starting in the correct state */
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
|
||||
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
|
||||
/*
|
||||
* The device requires two clocks while ENX is high before a serial
|
||||
* transaction. This is not clearly documented.
|
||||
*/
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
/* start transaction by bringing ENX low */
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
|
||||
while (bits--) {
|
||||
if (data & msb)
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
|
||||
gpio_set(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
else
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
|
||||
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
data <<= 1;
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
}
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
bits = 16;
|
||||
data = 0;
|
||||
/* set SDATA line as input */
|
||||
GPIO3_DIR &= ~PIN_MIXER_SDATA;
|
||||
GPIO_DIR(PORT_MIXER_SDATA) &= ~PIN_MIXER_SDATA;
|
||||
|
||||
while (bits--) {
|
||||
data <<= 1;
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
if (MIXER_SDATA_STATE)
|
||||
data |= 1;
|
||||
}
|
||||
/* set SDATA line as output */
|
||||
GPIO3_DIR |= PIN_MIXER_SDATA;
|
||||
GPIO_DIR(PORT_MIXER_SDATA) |= PIN_MIXER_SDATA;
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
|
||||
/*
|
||||
* The device requires a clock while ENX is high after a serial
|
||||
* transaction. This is not clearly documented.
|
||||
*/
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
return data;
|
||||
#endif /* DEBUG */
|
||||
@ -272,44 +280,54 @@ void rffc5071_spi_write(uint8_t r, uint16_t v) {
|
||||
uint32_t data = ((r & 0x7f) << 16) | v;
|
||||
|
||||
/* make sure everything is starting in the correct state */
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER, (PIN_MIXER_SCLK | PIN_MIXER_SDATA));
|
||||
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
|
||||
/*
|
||||
* The device requires two clocks while ENX is high before a serial
|
||||
* transaction. This is not clearly documented.
|
||||
*/
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
/* start transaction by bringing ENX low */
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_clear(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
|
||||
while (bits--) {
|
||||
if (data & msb)
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SDATA);
|
||||
gpio_set(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
else
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SDATA);
|
||||
gpio_clear(PORT_MIXER_SDATA, PIN_MIXER_SDATA);
|
||||
data <<= 1;
|
||||
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER, PIN_MIXER_SCLK);
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
}
|
||||
|
||||
gpio_set(PORT_MIXER_ENX, PIN_MIXER_ENX);
|
||||
|
||||
/*
|
||||
* The device requires a clock while ENX is high after a serial
|
||||
* transaction. This is not clearly documented.
|
||||
*/
|
||||
serial_delay();
|
||||
gpio_set(PORT_MIXER, PIN_MIXER_ENX);
|
||||
gpio_set(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
|
||||
serial_delay();
|
||||
gpio_clear(PORT_MIXER_SCLK, PIN_MIXER_SCLK);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -349,26 +367,58 @@ void rffc5071_regs_commit(void)
|
||||
}
|
||||
}
|
||||
|
||||
void rffc5071_tx(void) {
|
||||
void rffc5071_tx(uint8_t gpo) {
|
||||
LOG("# rffc5071_tx\n");
|
||||
set_RFFC5071_ENBL(0);
|
||||
set_RFFC5071_FULLD(0);
|
||||
set_RFFC5071_MODE(0); /* mixer 1 only (TX) */
|
||||
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
|
||||
#ifdef JAWBREAKER
|
||||
/* honor SWITCHCTRL_AMP_BYPASS and SWITCHCTRL_HP settings from caller */
|
||||
gpo &= (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
|
||||
if ((gpo & SWITCHCTRL_AMP_BYPASS) == SWITCHCTRL_AMP_BYPASS)
|
||||
gpo |= SWITCHCTRL_NO_TX_AMP_PWR;
|
||||
gpo |= (SWITCHCTRL_TX | SWITCHCTRL_NO_RX_AMP_PWR);
|
||||
rffc5071_set_gpo(gpo);
|
||||
#endif
|
||||
rffc5071_regs_commit();
|
||||
|
||||
rffc5071_enable();
|
||||
#ifdef JAWBREAKER
|
||||
/* honor SWITCHCTRL_MIX_BYPASS setting from caller */
|
||||
if ((gpo & SWITCHCTRL_MIX_BYPASS) == SWITCHCTRL_MIX_BYPASS)
|
||||
rffc5071_disable();
|
||||
else
|
||||
#endif
|
||||
rffc5071_enable();
|
||||
}
|
||||
|
||||
void rffc5071_rx(void) {
|
||||
void rffc5071_rx(uint8_t gpo) {
|
||||
LOG("# rfc5071_rx\n");
|
||||
set_RFFC5071_ENBL(0);
|
||||
set_RFFC5071_FULLD(0);
|
||||
set_RFFC5071_MODE(1); /* mixer 2 only (RX) */
|
||||
set_RFFC5071_MODE(1); /* mixer 2 used for both RX and TX */
|
||||
#ifdef JAWBREAKER
|
||||
/* honor SWITCHCTRL_AMP_BYPASS and SWITCHCTRL_HP settings from caller */
|
||||
gpo &= (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
|
||||
if ((gpo & SWITCHCTRL_AMP_BYPASS) == SWITCHCTRL_AMP_BYPASS)
|
||||
gpo |= SWITCHCTRL_NO_RX_AMP_PWR;
|
||||
gpo |= SWITCHCTRL_NO_TX_AMP_PWR;
|
||||
rffc5071_set_gpo(gpo);
|
||||
#endif
|
||||
rffc5071_regs_commit();
|
||||
|
||||
rffc5071_enable();
|
||||
#ifdef JAWBREAKER
|
||||
/* honor SWITCHCTRL_MIX_BYPASS setting from caller */
|
||||
if ((gpo & SWITCHCTRL_MIX_BYPASS) == SWITCHCTRL_MIX_BYPASS)
|
||||
rffc5071_disable();
|
||||
else
|
||||
#endif
|
||||
rffc5071_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* This function turns on both mixer (full-duplex) on the RFFC5071, but our
|
||||
* current hardware designs do not support full-duplex operation.
|
||||
*/
|
||||
void rffc5071_rxtx(void) {
|
||||
LOG("# rfc5071_rxtx\n");
|
||||
set_RFFC5071_ENBL(0);
|
||||
@ -433,14 +483,14 @@ uint16_t rffc5071_config_synth_int(uint16_t lo) {
|
||||
lo, n_lo, lodiv, fvco, fbkdiv, n, tune_freq);
|
||||
|
||||
/* Path 1 */
|
||||
set_RFFC5071_P1LODIV(lodiv);
|
||||
set_RFFC5071_P1LODIV(n_lo);
|
||||
set_RFFC5071_P1N(n);
|
||||
set_RFFC5071_P1PRESC(fbkdiv >> 1);
|
||||
set_RFFC5071_P1NMSB(0);
|
||||
set_RFFC5071_P1NLSB(0);
|
||||
|
||||
/* Path 2 */
|
||||
set_RFFC5071_P2LODIV(lodiv);
|
||||
set_RFFC5071_P2LODIV(n_lo);
|
||||
set_RFFC5071_P2N(n);
|
||||
set_RFFC5071_P2PRESC(fbkdiv >> 1);
|
||||
set_RFFC5071_P2NMSB(0);
|
||||
@ -468,6 +518,15 @@ uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz) {
|
||||
return tune_freq;
|
||||
}
|
||||
|
||||
void rffc5071_set_gpo(uint8_t gpo)
|
||||
{
|
||||
/* We set GPO for both paths just in case. */
|
||||
set_RFFC5071_P1GPO(gpo);
|
||||
set_RFFC5071_P2GPO(gpo);
|
||||
|
||||
rffc5071_regs_commit();
|
||||
}
|
||||
|
||||
#ifdef TEST
|
||||
int main(int ac, char **av)
|
||||
{
|
||||
|
||||
@ -31,6 +31,25 @@ extern uint32_t rffc5071_regs_dirty;
|
||||
#define RFFC5071_REG_SET_CLEAN(r) rffc5071_regs_dirty &= ~(1UL<<r)
|
||||
#define RFFC5071_REG_SET_DIRTY(r) rffc5071_regs_dirty |= (1UL<<r)
|
||||
|
||||
#ifdef JAWBREAKER
|
||||
/*
|
||||
* RF switches on Jawbreaker are controlled by General Purpose Outputs (GPO) on
|
||||
* the RFFC5072.
|
||||
*/
|
||||
#define SWITCHCTRL_NO_TX_AMP_PWR (1 << 0) /* turn off TX amp power */
|
||||
#define SWITCHCTRL_AMP_BYPASS (1 << 1) /* bypass amp section */
|
||||
#define SWITCHCTRL_TX (1 << 2) /* 1 for TX mode, 0 for RX mode */
|
||||
#define SWITCHCTRL_MIX_BYPASS (1 << 3) /* bypass RFFC5072 mixer section */
|
||||
#define SWITCHCTRL_HP (1 << 4) /* 1 for high-pass, 0 for low-pass */
|
||||
#define SWITCHCTRL_NO_RX_AMP_PWR (1 << 5) /* turn off RX amp power */
|
||||
|
||||
/*
|
||||
* Safe (initial) switch settings turn off both amplifiers and enable both amp
|
||||
* bypass and mixer bypass.
|
||||
*/
|
||||
#define SWITCHCTRL_SAFE (SWITCHCTRL_NO_TX_AMP_PWR | SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_TX | SWITCHCTRL_MIX_BYPASS | SWITCHCTRL_HP | SWITCHCTRL_NO_RX_AMP_PWR)
|
||||
#endif
|
||||
|
||||
/* Initialize chip. Call _setup() externally, as it calls _init(). */
|
||||
extern void rffc5071_init(void);
|
||||
extern void rffc5071_setup(void);
|
||||
@ -56,10 +75,12 @@ extern uint16_t rffc5071_set_frequency(uint16_t mhz, uint32_t hz);
|
||||
|
||||
/* Set up rx only, tx only, or full duplex. Chip should be disabled
|
||||
* before _tx, _rx, or _rxtx are called. */
|
||||
extern void rffc5071_tx(void);
|
||||
extern void rffc5071_rx(void);
|
||||
extern void rffc5071_tx(uint8_t);
|
||||
extern void rffc5071_rx(uint8_t);
|
||||
extern void rffc5071_rxtx(void);
|
||||
extern void rffc5071_enable(void);
|
||||
extern void rffc5071_disable(void);
|
||||
|
||||
extern void rffc5071_set_gpo(uint8_t);
|
||||
|
||||
#endif // __RFFC5071_H
|
||||
|
||||
@ -161,6 +161,7 @@ void si5351c_configure_multisynth(const uint_fast8_t ms_number,
|
||||
si5351c_write(data, sizeof(data));
|
||||
}
|
||||
|
||||
#ifdef JELLYBEAN
|
||||
/*
|
||||
* Registers 16 through 23: CLKx Control
|
||||
* CLK0:
|
||||
@ -211,6 +212,66 @@ void si5351c_configure_clock_control()
|
||||
uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x0F, 0x4F, 0xC0, 0xC0 };
|
||||
si5351c_write(data, sizeof(data));
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef JAWBREAKER
|
||||
/*
|
||||
* Registers 16 through 23: CLKx Control
|
||||
* CLK0:
|
||||
* CLK0_PDN=0 (powered up)
|
||||
* MS0_INT=1 (integer mode)
|
||||
* MS0_SRC=0 (PLLA as source for MultiSynth 0)
|
||||
* CLK0_INV=0 (not inverted)
|
||||
* CLK0_SRC=3 (MS0 as input source)
|
||||
* CLK0_IDRV=3 (8mA)
|
||||
* CLK1:
|
||||
* CLK1_PDN=0 (powered up)
|
||||
* MS1_INT=1 (integer mode)
|
||||
* MS1_SRC=0 (PLLA as source for MultiSynth 1)
|
||||
* CLK1_INV=0 (not inverted)
|
||||
* CLK1_SRC=2 (MS0 as input source)
|
||||
* CLK1_IDRV=3 (8mA)
|
||||
* CLK2:
|
||||
* CLK2_PDN=0 (powered up)
|
||||
* MS2_INT=1 (integer mode)
|
||||
* MS2_SRC=0 (PLLA as source for MultiSynth 2)
|
||||
* CLK2_INV=0 (not inverted)
|
||||
* CLK2_SRC=2 (MS0 as input source)
|
||||
* CLK2_IDRV=3 (8mA)
|
||||
* CLK3:
|
||||
* CLK3_PDN=0 (powered up)
|
||||
* MS3_INT=1 (integer mode)
|
||||
* MS3_SRC=0 (PLLA as source for MultiSynth 3)
|
||||
* CLK3_INV=0 (inverted)
|
||||
* CLK3_SRC=2 (MS0 as input source)
|
||||
* CLK3_IDRV=3 (8mA)
|
||||
* CLK4:
|
||||
* CLK4_PDN=0 (powered up)
|
||||
* MS4_INT=1 (integer mode)
|
||||
* MS4_SRC=0 (PLLA as source for MultiSynth 4)
|
||||
* CLK4_INV=0 (not inverted)
|
||||
* CLK4_SRC=3 (MS4 as input source)
|
||||
* CLK4_IDRV=3 (8mA)
|
||||
* CLK5:
|
||||
* CLK5_PDN=0 (powered up)
|
||||
* MS5_INT=1 (integer mode)
|
||||
* MS5_SRC=0 (PLLA as source for MultiSynth 5)
|
||||
* CLK5_INV=0 (not inverted)
|
||||
* CLK5_SRC=3 (MS5 as input source)
|
||||
* CLK5_IDRV=3 (8mA)
|
||||
* CLK6: (not connected)
|
||||
* CLK5_PDN=1 (powered down)
|
||||
* MS5_INT=1 (integer mode)
|
||||
* CLK7: (not connected)
|
||||
* CLK7_PDN=1 (powered down)
|
||||
* MS7_INT=0 (fractional mode -- to support 12MHz to LPC)
|
||||
*/
|
||||
void si5351c_configure_clock_control()
|
||||
{
|
||||
uint8_t data[] = { 16, 0x4F, 0x4B, 0x4B, 0x4B, 0x4F, 0x4F, 0xC0, 0x80 };
|
||||
si5351c_write(data, sizeof(data));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable CLK outputs 0, 1, 2, 3, 4, 5 only. */
|
||||
void si5351c_enable_clock_outputs()
|
||||
|
||||
@ -265,6 +265,7 @@ void configure_sgpio_test_rx() {
|
||||
int main(void) {
|
||||
|
||||
const uint32_t freq = 2700000000U;
|
||||
uint8_t switchctrl = 0;
|
||||
|
||||
pin_setup();
|
||||
enable_1v8_power();
|
||||
@ -280,29 +281,11 @@ int main(void) {
|
||||
ssp1_set_mode_max2837();
|
||||
max2837_setup();
|
||||
rffc5071_setup();
|
||||
rffc5071_rx();
|
||||
rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
|
||||
|
||||
#ifdef LOLLIPOP_SWITCH_SET_UP_DONE_IN_RFFC5071
|
||||
/* lollipop */
|
||||
uint8_t gpo =
|
||||
(1 << 0) /* SWTXB1 (!tx_bypass) */
|
||||
| (0 << 1) /* SWRXB1 (rx_bypass) */
|
||||
| (1 << 2) /* SWTXA1 (tx_hp) */
|
||||
| (0 << 3) /* unused */
|
||||
| (1 << 4) /* SWRXA1 (rx_hp) */
|
||||
| (0 << 5); /* SWD1 (!tx_ant) */
|
||||
/* licorice */
|
||||
//uint8_t gpo =
|
||||
//(0 << 0) /* MIX_BYPASS */
|
||||
//| (0 << 1) /* AMP_BYPASS */
|
||||
//| (0 << 2) /* TX */
|
||||
//| (0 << 3) /* unused */
|
||||
//| (0 << 4) /* HP */
|
||||
//| (0 << 5); /* !AMP_PWR */
|
||||
rffc5071_reg_write(RFFC5071_GPO, (gpo << 9) | (gpo << 2) | 0x3);
|
||||
gpio_set(PORT_LED1_3, (PIN_LED1)); /* LED1 on */
|
||||
#ifdef JAWBREAKER
|
||||
switchctrl = (SWITCHCTRL_AMP_BYPASS | SWITCHCTRL_HP);
|
||||
#endif
|
||||
rffc5071_rx(switchctrl);
|
||||
rffc5071_set_frequency(500, 0); // 500 MHz, 0 Hz (Hz ignored)
|
||||
|
||||
max2837_set_frequency(freq);
|
||||
max2837_start();
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
EESchema Schematic File Version 2 date Fri Sep 7 01:59:43 2012
|
||||
EESchema Schematic File Version 2 date Sat Sep 22 23:30:21 2012
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
@ -37,7 +37,7 @@ $Descr User 17000 11000
|
||||
encoding utf-8
|
||||
Sheet 2 4
|
||||
Title ""
|
||||
Date "7 sep 2012"
|
||||
Date "23 sep 2012"
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
@ -45,6 +45,18 @@ Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L C C53
|
||||
U 1 1 5054932E
|
||||
P 10150 8450
|
||||
F 0 "C53" H 10200 8550 50 0000 L CNN
|
||||
F 1 "1uF" H 10200 8350 50 0000 L CNN
|
||||
F 4 "Taiyo Yuden" H 10150 8450 60 0001 C CNN "Manufacturer"
|
||||
F 5 "LMK105BJ105KV-F" H 10150 8450 60 0001 C CNN "Part Number"
|
||||
F 6 "CAP CER 1UF 10V 10% X5R 0402" H 10150 8450 60 0001 C CNN "Description"
|
||||
1 10150 8450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 5700 1550 3 40 ~ 0
|
||||
!RX_AMP_PWR
|
||||
Text Label 4650 800 0 40 ~ 0
|
||||
@ -1010,17 +1022,18 @@ U 1 1 50452C20
|
||||
P 14750 9600
|
||||
F 0 "J2" H 15050 9700 60 0000 C CNN
|
||||
F 1 "900MHZ-F-ANTENNA" H 15000 10250 60 0000 C CNN
|
||||
F 4 "DNP" H 14750 9600 60 0001 C CNN "Note"
|
||||
1 14750 9600
|
||||
0 -1 -1 0
|
||||
$EndComp
|
||||
Text GLabel 7200 4750 2 40 Input ~ 0
|
||||
RESETX
|
||||
MIXER_RESETX
|
||||
Text GLabel 7200 4650 2 40 Input ~ 0
|
||||
ENX
|
||||
MIXER_ENX
|
||||
Text GLabel 7200 4550 2 40 Input ~ 0
|
||||
SSP1_SCK
|
||||
MIXER_SCLK
|
||||
Text GLabel 7200 4450 2 40 Input ~ 0
|
||||
SSP1_MOSI
|
||||
MIXER_SDATA
|
||||
Text Label 5000 4450 1 40 ~ 0
|
||||
TX
|
||||
Text GLabel 7350 9100 1 40 Input ~ 0
|
||||
@ -1101,7 +1114,7 @@ P 14050 6250
|
||||
F 0 "U25" H 14050 6300 60 0000 C CNN
|
||||
F 1 "MGA-81563" H 14050 6200 60 0000 C CNN
|
||||
F 4 "Avago" H 14050 6250 60 0001 C CNN "Manufacturer"
|
||||
F 5 "MGA-81563" H 14050 6250 60 0001 C CNN "Part Number"
|
||||
F 5 "MGA-81563-TR1G" H 14050 6250 60 0001 C CNN "Part Number"
|
||||
F 6 "0.1-6 GHz 3 V, 14 dBm Amplifier" H 14050 6250 60 0001 C CNN "Description"
|
||||
1 14050 6250
|
||||
-1 0 0 1
|
||||
@ -1136,9 +1149,9 @@ U 1 1 503BF2DA
|
||||
P 13350 6650
|
||||
F 0 "C161" H 13400 6750 50 0000 L CNN
|
||||
F 1 "1uF" H 13400 6550 50 0000 L CNN
|
||||
F 4 "Murata" H 13350 6650 60 0001 C CNN "Manufacturer"
|
||||
F 5 "GRM155R61A105ME15D" H 13350 6650 60 0001 C CNN "Part Number"
|
||||
F 6 "CAP CER 1UF 10V 20% X5R 0402" H 13350 6650 60 0001 C CNN "Description"
|
||||
F 4 "Taiyo Yuden" H 13350 6650 60 0001 C CNN "Manufacturer"
|
||||
F 5 "LMK105BJ105KV-F" H 13350 6650 60 0001 C CNN "Part Number"
|
||||
F 6 "CAP CER 1UF 10V 10% X5R 0402" H 13350 6650 60 0001 C CNN "Description"
|
||||
1 13350 6650
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
@ -1803,7 +1816,7 @@ P 9450 9750
|
||||
F 0 "U13" H 9450 9800 60 0000 C CNN
|
||||
F 1 "MGA-81563" H 9450 9700 60 0000 C CNN
|
||||
F 4 "Avago" H 9450 9750 60 0001 C CNN "Manufacturer"
|
||||
F 5 "MGA-81563" H 9450 9750 60 0001 C CNN "Part Number"
|
||||
F 5 "MGA-81563-TR1G" H 9450 9750 60 0001 C CNN "Part Number"
|
||||
F 6 "0.1-6 GHz 3 V, 14 dBm Amplifier" H 9450 9750 60 0001 C CNN "Description"
|
||||
1 9450 9750
|
||||
1 0 0 -1
|
||||
@ -1827,18 +1840,6 @@ F 1 "GND" H 10150 9480 30 0001 C CNN
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L C C53
|
||||
U 1 1 502C6DB4
|
||||
P 10150 8450
|
||||
F 0 "C53" H 10200 8550 50 0000 L CNN
|
||||
F 1 "1uF" H 10200 8350 50 0000 L CNN
|
||||
F 4 "Murata" H 10150 8450 60 0001 C CNN "Manufacturer"
|
||||
F 5 "GRM155R61A105ME15D" H 10150 8450 60 0001 C CNN "Part Number"
|
||||
F 6 "CAP CER 1UF 10V 20% X5R 0402" H 10150 8450 60 0001 C CNN "Description"
|
||||
1 10150 8450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L C C64
|
||||
U 1 1 502C6D4A
|
||||
P 15300 8600
|
||||
@ -1905,7 +1906,7 @@ P 5350 3100
|
||||
F 0 "U4" H 5350 3200 60 0000 C CNN
|
||||
F 1 "RFFC5072" H 5350 3000 60 0000 C CNN
|
||||
F 4 "RFMD" H 5350 3100 60 0001 C CNN "Manufacturer"
|
||||
F 5 "RFFC5072" H 5350 3100 60 0001 C CNN "Part Number"
|
||||
F 5 "RFFC5072TR7" H 5350 3100 60 0001 C CNN "Part Number"
|
||||
F 6 "WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER" H 5350 3100 60 0001 C CNN "Description"
|
||||
1 5350 3100
|
||||
-1 0 0 1
|
||||
@ -2915,8 +2916,8 @@ U 1 1 4FAEC8AD
|
||||
P 8400 2050
|
||||
F 0 "C14" H 8450 2150 50 0000 L CNN
|
||||
F 1 "8p2" H 8450 1950 50 0000 L CNN
|
||||
F 4 "Murata" H 8400 2050 60 0001 C CNN "Manufacturer"
|
||||
F 5 "GJM1555C1H8R2CB01D" H 8400 2050 60 0001 C CNN "Part Number"
|
||||
F 4 "Taiyo Yuden" H 8400 2050 60 0001 C CNN "Manufacturer"
|
||||
F 5 "UMK105CG8R2DV-F" H 8400 2050 60 0001 C CNN "Part Number"
|
||||
F 6 "CAP CER 8.2PF 50V NP0 0402" H 8400 2050 60 0001 C CNN "Description"
|
||||
1 8400 2050
|
||||
1 0 0 -1
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
EESchema-LIBRARY Version 2.3 Date: Fri Sep 7 01:59:43 2012
|
||||
EESchema-LIBRARY Version 2.3 Date: Sat Sep 22 23:30:21 2012
|
||||
#encoding utf-8
|
||||
#
|
||||
# +1.8V
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
Cmp-Mod V01 Created by CvPcb (2012-05-21 BZR 3261)-stable date = Thu Sep 6 10:57:34 2012
|
||||
Cmp-Mod V01 Created by CvPcb (2012-05-21 BZR 3261)-stable date = Thu Sep 13 21:53:05 2012
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /503BB638/4FAECB99;
|
||||
@ -819,6 +819,13 @@ ValeurCmp = C;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A7BD;
|
||||
Reference = C118;
|
||||
ValeurCmp = DNP;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/503C49AF;
|
||||
Reference = C119;
|
||||
@ -1088,14 +1095,14 @@ EndCmp
|
||||
BeginCmp
|
||||
TimeStamp = /5037043E/50370ED5;
|
||||
Reference = C157;
|
||||
ValeurCmp = 10pF;
|
||||
ValeurCmp = 18pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /5037043E/50370ED2;
|
||||
TimeStamp = /5037043E/5052A211;
|
||||
Reference = C158;
|
||||
ValeurCmp = 10pF;
|
||||
ValeurCmp = 18pF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
@ -1134,6 +1141,20 @@ ValeurCmp = 10nF;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A87B;
|
||||
Reference = C164;
|
||||
ValeurCmp = DNP;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A87E;
|
||||
Reference = C165;
|
||||
ValeurCmp = DNP;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /503BB638/4FB3F9B0;
|
||||
Reference = D1;
|
||||
@ -1568,6 +1589,41 @@ ValeurCmp = VAA;
|
||||
IdModule = GSG-HEADER-1x2-SHORTED;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A309;
|
||||
Reference = P37;
|
||||
ValeurCmp = SCL;
|
||||
IdModule = GSG-TESTPOINT-50MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A32D;
|
||||
Reference = P38;
|
||||
ValeurCmp = SDA;
|
||||
IdModule = GSG-TESTPOINT-50MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A332;
|
||||
Reference = P39;
|
||||
ValeurCmp = SSP1_SCK;
|
||||
IdModule = GSG-TESTPOINT-50MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A336;
|
||||
Reference = P40;
|
||||
ValeurCmp = SSP1_MOSI;
|
||||
IdModule = GSG-TESTPOINT-50MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A335;
|
||||
Reference = P41;
|
||||
ValeurCmp = SSP1_MISO;
|
||||
IdModule = GSG-TESTPOINT-50MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /503BB638/502E69D1;
|
||||
Reference = Q1;
|
||||
@ -1890,6 +1946,13 @@ ValeurCmp = 0;
|
||||
IdModule = GSG-0402-SHORT-20MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A8A8;
|
||||
Reference = R45;
|
||||
ValeurCmp = DNP;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /5037043E/503F8429;
|
||||
Reference = R46;
|
||||
@ -2156,6 +2219,20 @@ ValeurCmp = 0;
|
||||
IdModule = GSG-0402-SHORT-10MIL;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A892;
|
||||
Reference = R84;
|
||||
ValeurCmp = 50;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A7D7;
|
||||
Reference = R85;
|
||||
ValeurCmp = DNP;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /5037043E/503F9874;
|
||||
Reference = R86;
|
||||
@ -2198,6 +2275,13 @@ ValeurCmp = 39;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /50370666/5052A841;
|
||||
Reference = R92;
|
||||
ValeurCmp = 50;
|
||||
IdModule = GSG-0402;
|
||||
EndCmp
|
||||
|
||||
BeginCmp
|
||||
TimeStamp = /5037043E/503F9958;
|
||||
Reference = R93;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
EESchema Schematic File Version 2 date Fri Sep 7 01:59:43 2012
|
||||
EESchema Schematic File Version 2 date Sat Sep 22 23:30:21 2012
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
@ -37,7 +37,7 @@ $Descr User 17000 11000
|
||||
encoding utf-8
|
||||
Sheet 1 4
|
||||
Title "jawbreaker"
|
||||
Date "7 sep 2012"
|
||||
Date "23 sep 2012"
|
||||
Rev ""
|
||||
Comp "Copyright 2012 Michael Ossmann"
|
||||
Comment1 "License: GPL v2"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
|
||||
PCBNEW-LibModule-V1 Thu Sep 6 10:38:14 2012
|
||||
PCBNEW-LibModule-V1 Thu Sep 20 14:22:18 2012
|
||||
# encoding utf-8
|
||||
$INDEX
|
||||
GSG-0402
|
||||
@ -37,6 +37,7 @@ GSG-HEADER-2x8
|
||||
GSG-HEADER-2x9
|
||||
GSG-HHM1595A1
|
||||
GSG-HOLE-12MIL
|
||||
GSG-HOLE126MIL
|
||||
GSG-HP-DEA
|
||||
GSG-LP0603
|
||||
GSG-LQFP144
|
||||
@ -8081,69 +8082,6 @@ Po -260 -395
|
||||
Le 65
|
||||
$EndPAD
|
||||
$EndMODULE GSG-SOT363
|
||||
$MODULE GSG-SKY13350-385LF
|
||||
Po 0 0 0 15 5032C4C2 00000000 ~~
|
||||
Li GSG-SKY13350-385LF
|
||||
Sc 00000000
|
||||
AR GSG-SKY13350-385LF
|
||||
Op 0 0 0
|
||||
T0 0 0 197 118 0 30 N V 21 N "GSG-SKY13350-385LF"
|
||||
T1 0 0 197 118 0 30 N I 21 N "VAL**"
|
||||
DC -236 -236 -197 -197 70 21
|
||||
DS 197 197 -197 197 70 21
|
||||
DS -197 197 -197 -197 70 21
|
||||
DS -197 -197 197 -197 70 21
|
||||
DS 197 -197 197 197 70 21
|
||||
$PAD
|
||||
Sh "1" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -211 -98
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "3" R 79 240 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 177
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "4" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 211 98
|
||||
Le 20
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "5" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 211 -98
|
||||
Le 4149
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "6" R 79 240 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 -177
|
||||
Le 41110432
|
||||
.SolderPasteRatio -0.04
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "2" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -211 98
|
||||
Le 839724792
|
||||
$EndPAD
|
||||
$EndMODULE GSG-SKY13350-385LF
|
||||
$MODULE GSG-SKY13317-373LF
|
||||
Po 0 0 0 15 5032C63B 00000000 ~~
|
||||
Li GSG-SKY13317-373LF
|
||||
@ -8538,8 +8476,25 @@ Ne 0 ""
|
||||
Po 0 0
|
||||
$EndPAD
|
||||
$EndMODULE GSG-0402-SHORT-20MIL
|
||||
$MODULE GSG-HOLE126MIL
|
||||
Po 0 0 0 15 5050D97F 00000000 ~~
|
||||
Li GSG-HOLE126MIL
|
||||
Sc 00000000
|
||||
AR GSG-HOLE260MIL
|
||||
Op 0 0 0
|
||||
T0 0 0 394 394 0 80 N V 21 N "HOLE126MIL"
|
||||
T1 0 0 394 394 0 80 N V 21 N "VAL**"
|
||||
$PAD
|
||||
Sh "" C 1260 1260 0 0 0
|
||||
Dr 1260 0 0
|
||||
At STD N 00C0FFFF
|
||||
Ne 0 ""
|
||||
Po 0 0
|
||||
Le 235021312
|
||||
$EndPAD
|
||||
$EndMODULE GSG-HOLE126MIL
|
||||
$MODULE GSG-HEADER-1x2-SHORTED
|
||||
Po 0 0 0 15 5048D16E 00000000 ~~
|
||||
Po 0 0 0 15 505B6DA1 00000000 ~~
|
||||
Li GSG-HEADER-1x2-SHORTED
|
||||
Kw CONN
|
||||
Sc 00000000
|
||||
@ -8574,9 +8529,72 @@ $EndPAD
|
||||
$PAD
|
||||
Sh "" R 600 100 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
At SMD N 00808000
|
||||
Ne 0 ""
|
||||
Po 0 0
|
||||
$EndPAD
|
||||
$EndMODULE GSG-HEADER-1x2-SHORTED
|
||||
$MODULE GSG-SKY13350-385LF
|
||||
Po 0 0 0 15 5032C4C2 00000000 ~~
|
||||
Li GSG-SKY13350-385LF
|
||||
Sc 00000000
|
||||
AR GSG-SKY13350-385LF
|
||||
Op 0 0 0
|
||||
.SolderPasteRatio -0.02
|
||||
T0 0 0 197 118 0 30 N V 21 N "GSG-SKY13350-385LF"
|
||||
T1 0 0 197 118 0 30 N I 21 N "VAL**"
|
||||
DC -236 -236 -197 -197 70 21
|
||||
DS 197 197 -197 197 70 21
|
||||
DS -197 197 -197 -197 70 21
|
||||
DS -197 -197 197 -197 70 21
|
||||
DS 197 -197 197 197 70 21
|
||||
$PAD
|
||||
Sh "1" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -211 -98
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "3" R 79 240 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 177
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "4" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 211 98
|
||||
Le 20
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "5" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 211 -98
|
||||
Le 4149
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "6" R 79 240 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po 0 -177
|
||||
Le 41110432
|
||||
$EndPAD
|
||||
$PAD
|
||||
Sh "2" R 169 60 0 0 0
|
||||
Dr 0 0 0
|
||||
At SMD N 00888000
|
||||
Ne 0 ""
|
||||
Po -211 98
|
||||
Le 839724792
|
||||
$EndPAD
|
||||
$EndMODULE GSG-SKY13350-385LF
|
||||
$EndLIBRARY
|
||||
|
||||
Reference in New Issue
Block a user