ssp1_set_mode_max2837()/void ssp1_set_mode_max5864(void) SPI speed updated to 4.857MHz instead of 0.0498MHz
To do test it to check there is no problem.
This commit is contained in:
@ -312,9 +312,15 @@ void ssp1_init(void)
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void ssp1_set_mode_max2837(void)
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void ssp1_set_mode_max2837(void)
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{
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{
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/* FIXME speed up once everything is working reliably */
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/* FIXME speed up once everything is working reliably */
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/*
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// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 32;
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const uint8_t serial_clock_rate = 32;
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const uint8_t clock_prescale_rate = 128;
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const uint8_t clock_prescale_rate = 128;
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*/
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// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 21;
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const uint8_t clock_prescale_rate = 2;
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ssp_init(SSP1_NUM,
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ssp_init(SSP1_NUM,
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SSP_DATA_16BITS,
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SSP_DATA_16BITS,
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SSP_FRAME_SPI,
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SSP_FRAME_SPI,
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@ -329,9 +335,15 @@ void ssp1_set_mode_max2837(void)
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void ssp1_set_mode_max5864(void)
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void ssp1_set_mode_max5864(void)
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{
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{
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/* FIXME speed up once everything is working reliably */
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/* FIXME speed up once everything is working reliably */
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/*
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// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 32;
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const uint8_t serial_clock_rate = 32;
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const uint8_t clock_prescale_rate = 128;
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const uint8_t clock_prescale_rate = 128;
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*/
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// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
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const uint8_t serial_clock_rate = 21;
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const uint8_t clock_prescale_rate = 2;
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ssp_init(SSP1_NUM,
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ssp_init(SSP1_NUM,
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SSP_DATA_8BITS,
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SSP_DATA_8BITS,
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SSP_FRAME_SPI,
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SSP_FRAME_SPI,
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