From d509489fffc6f916a8e1a0332cf74e9f87d77eea Mon Sep 17 00:00:00 2001 From: TitanMKD Date: Wed, 20 Mar 2013 22:20:47 +0100 Subject: [PATCH] ssp1_set_mode_max2837()/void ssp1_set_mode_max5864(void) SPI speed updated to 4.857MHz instead of 0.0498MHz To do test it to check there is no problem. --- firmware/common/hackrf_core.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index d1e7e0b7..0b719ccf 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -312,9 +312,15 @@ void ssp1_init(void) void ssp1_set_mode_max2837(void) { /* FIXME speed up once everything is working reliably */ + /* + // Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz const uint8_t serial_clock_rate = 32; const uint8_t clock_prescale_rate = 128; - + */ + // Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz + const uint8_t serial_clock_rate = 21; + const uint8_t clock_prescale_rate = 2; + ssp_init(SSP1_NUM, SSP_DATA_16BITS, SSP_FRAME_SPI, @@ -329,9 +335,15 @@ void ssp1_set_mode_max2837(void) void ssp1_set_mode_max5864(void) { /* FIXME speed up once everything is working reliably */ + /* + // Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz const uint8_t serial_clock_rate = 32; const uint8_t clock_prescale_rate = 128; - + */ + // Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz + const uint8_t serial_clock_rate = 21; + const uint8_t clock_prescale_rate = 2; + ssp_init(SSP1_NUM, SSP_DATA_8BITS, SSP_FRAME_SPI,