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hack(rad1o): Lower noise configuration

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This commit is contained in:
Tobias Schneider
2015-12-05 23:46:59 +01:00
parent 4ba474807f
commit 9e827b56be
3 changed files with 40 additions and 11 deletions
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6
firmware/common/hackrf_core.c
View File

@ -346,20 +346,18 @@ void cpu_clock_init(void)
si5351c_configure_multisynth(4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS5/CLK5 is the source for the RFFC5071 mixer. */ /* MS5/CLK5 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(5, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */ si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */ /* MS6/CLK6 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */ /* MS7/CLK7 is the source for the LPC43xx microcontroller. */
#if 0
/* Clock is deactivated as it is not used and creates noise */
uint8_t ms7data[] = { 90, 255, 20, 0 }; uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(ms7data, sizeof(ms7data)); si5351c_write(ms7data, sizeof(ms7data));
#endif
#endif #endif
/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */ /* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
sample_rate_set(10000000); sample_rate_set(10000000);
//sample_rate_set(8000000);
si5351c_set_clock_source(PLL_SOURCE_XTAL); si5351c_set_clock_source(PLL_SOURCE_XTAL);
// soft reset // soft reset

10
firmware/common/max2871.c
View File

@ -68,7 +68,7 @@ void mixer_setup(void)
max2871_set_MUX(0x0C); // Register 6 readback max2871_set_MUX(0x0C); // Register 6 readback
max2871_set_DBR(0); max2871_set_DBR(0);
max2871_set_RDIV2(0); max2871_set_RDIV2(0);
max2871_set_R(1); // 50 MHz f_PFD max2871_set_R(1); // 40 MHz f_PFD
max2871_set_REG4DB(1); max2871_set_REG4DB(1);
max2871_set_CP(15); // ?: CP charge pump current 0-15 max2871_set_CP(15); // ?: CP charge pump current 0-15
max2871_set_LDF(1); // INT-N max2871_set_LDF(1); // INT-N
@ -87,7 +87,7 @@ void mixer_setup(void)
max2871_set_SDLDO(0); max2871_set_SDLDO(0);
max2871_set_SDDIV(0); max2871_set_SDDIV(0);
max2871_set_SDREF(0); max2871_set_SDREF(0);
max2871_set_BS(20*50); // For 50 MHz f_PFD max2871_set_BS(20*40); // For 40 MHz f_PFD
max2871_set_FB(1); // Do not put DIVA into the feedback loop max2871_set_FB(1); // Do not put DIVA into the feedback loop
max2871_set_DIVA(0); max2871_set_DIVA(0);
max2871_set_SDVCO(0); max2871_set_SDVCO(0);
@ -207,10 +207,10 @@ static void max2871_write_registers(void)
/* Set frequency (MHz). */ /* Set frequency (MHz). */
uint64_t mixer_set_frequency(uint16_t mhz) uint64_t mixer_set_frequency(uint16_t mhz)
{ {
int n = mhz / 50; int n = mhz / 40;
int diva = 0; int diva = 0;
while(n * 50 < 3000) { while(n * 40 < 3000) {
n *= 2; n *= 2;
diva += 1; diva += 1;
} }
@ -227,7 +227,7 @@ uint64_t mixer_set_frequency(uint16_t mhz)
max2871_set_RFA_EN(1); max2871_set_RFA_EN(1);
max2871_write_registers(); max2871_write_registers();
return (mhz/50)*50 * 1000000; return (mhz/40)*40 * 1000000;
} }
void mixer_tx(void) void mixer_tx(void)

35
firmware/common/si5351c.c
View File

@ -239,7 +239,7 @@ void si5351c_configure_clock_control()
} }
#endif #endif
#if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O) #if (defined JAWBREAKER || defined HACKRF_ONE)
void si5351c_configure_clock_control(const enum pll_sources source) void si5351c_configure_clock_control(const enum pll_sources source)
{ {
uint8_t pll; uint8_t pll;
@ -265,10 +265,41 @@ void si5351c_configure_clock_control(const enum pll_sources source)
} }
#endif #endif
/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ #ifdef RAD1O
void si5351c_configure_clock_control(const enum pll_sources source)
{
uint8_t pll;
/* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A;
/* Clock to CPU is deactivated as it is not used and creates noise */
/* External clock output is deactivated as it is not used and creates noise */
uint8_t data[] = {16
,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
};
si5351c_write(data, sizeof(data));
}
#endif
void si5351c_enable_clock_outputs() void si5351c_enable_clock_outputs()
{ {
#ifdef RAD1O
/* Enable CLK outputs 0, 1, 2, 4, 5 only. */
/* 7: Clock to CPU is deactivated as it is not used and creates noise */
/* 3: External clock output is deactivated as it is not used and creates noise */
uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
#else
/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
uint8_t data[] = { 3, 0x40 }; uint8_t data[] = { 3, 0x40 };
#endif
si5351c_write(data, sizeof(data)); si5351c_write(data, sizeof(data));
} }