From 9e827b56beebf0ac512da514b968fafc7410c618 Mon Sep 17 00:00:00 2001 From: Tobias Schneider Date: Sat, 5 Dec 2015 23:46:59 +0100 Subject: [PATCH] hack(rad1o): Lower noise configuration --- firmware/common/hackrf_core.c | 6 ++---- firmware/common/max2871.c | 10 +++++----- firmware/common/si5351c.c | 35 +++++++++++++++++++++++++++++++++-- 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index 422d4606..16760e17 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -346,20 +346,18 @@ void cpu_clock_init(void) si5351c_configure_multisynth(4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS5/CLK5 is the source for the RFFC5071 mixer. */ - si5351c_configure_multisynth(5, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */ + si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS6/CLK6 is unused. */ /* MS7/CLK7 is the source for the LPC43xx microcontroller. */ -#if 0 - /* Clock is deactivated as it is not used and creates noise */ uint8_t ms7data[] = { 90, 255, 20, 0 }; si5351c_write(ms7data, sizeof(ms7data)); -#endif #endif /* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */ sample_rate_set(10000000); + //sample_rate_set(8000000); si5351c_set_clock_source(PLL_SOURCE_XTAL); // soft reset diff --git a/firmware/common/max2871.c b/firmware/common/max2871.c index a58a3a49..095891b0 100644 --- a/firmware/common/max2871.c +++ b/firmware/common/max2871.c @@ -68,7 +68,7 @@ void mixer_setup(void) max2871_set_MUX(0x0C); // Register 6 readback max2871_set_DBR(0); max2871_set_RDIV2(0); - max2871_set_R(1); // 50 MHz f_PFD + max2871_set_R(1); // 40 MHz f_PFD max2871_set_REG4DB(1); max2871_set_CP(15); // ?: CP charge pump current 0-15 max2871_set_LDF(1); // INT-N @@ -87,7 +87,7 @@ void mixer_setup(void) max2871_set_SDLDO(0); max2871_set_SDDIV(0); max2871_set_SDREF(0); - max2871_set_BS(20*50); // For 50 MHz f_PFD + max2871_set_BS(20*40); // For 40 MHz f_PFD max2871_set_FB(1); // Do not put DIVA into the feedback loop max2871_set_DIVA(0); max2871_set_SDVCO(0); @@ -207,10 +207,10 @@ static void max2871_write_registers(void) /* Set frequency (MHz). */ uint64_t mixer_set_frequency(uint16_t mhz) { - int n = mhz / 50; + int n = mhz / 40; int diva = 0; - while(n * 50 < 3000) { + while(n * 40 < 3000) { n *= 2; diva += 1; } @@ -227,7 +227,7 @@ uint64_t mixer_set_frequency(uint16_t mhz) max2871_set_RFA_EN(1); max2871_write_registers(); - return (mhz/50)*50 * 1000000; + return (mhz/40)*40 * 1000000; } void mixer_tx(void) diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c index e01b3659..10598739 100644 --- a/firmware/common/si5351c.c +++ b/firmware/common/si5351c.c @@ -239,7 +239,7 @@ void si5351c_configure_clock_control() } #endif -#if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O) +#if (defined JAWBREAKER || defined HACKRF_ONE) void si5351c_configure_clock_control(const enum pll_sources source) { uint8_t pll; @@ -265,10 +265,41 @@ void si5351c_configure_clock_control(const enum pll_sources source) } #endif -/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ +#ifdef RAD1O +void si5351c_configure_clock_control(const enum pll_sources source) +{ + uint8_t pll; + + /* PLLA on XTAL */ + pll = SI5351C_CLK_PLL_SRC_A; + + /* Clock to CPU is deactivated as it is not used and creates noise */ + /* External clock output is deactivated as it is not used and creates noise */ + uint8_t data[] = {16 + ,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) + ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) + ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ + ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ + }; + si5351c_write(data, sizeof(data)); +} +#endif + void si5351c_enable_clock_outputs() { +#ifdef RAD1O + /* Enable CLK outputs 0, 1, 2, 4, 5 only. */ + /* 7: Clock to CPU is deactivated as it is not used and creates noise */ + /* 3: External clock output is deactivated as it is not used and creates noise */ + uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))}; +#else + /* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ uint8_t data[] = { 3, 0x40 }; +#endif si5351c_write(data, sizeof(data)); }