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Merge pull request #355 from dominicgs/firmware_cleanup

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Firmware cleanup
This commit is contained in:
Michael Ossmann
2017-02-28 16:03:15 -07:00
committed by GitHub
parent c2e775b1b9 8b853266ef
commit 9bbbbbfbfb
13 changed files with 102 additions and 2645 deletions
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2
firmware/common/LPC4330_M4_memory.ld
View File

@ -20,7 +20,7 @@
* Boston, MA 02110-1301, USA. * Boston, MA 02110-1301, USA.
*/ */
/* Linker script for HackRF Jellybean/Jawbreaker (LPC4330, 1M SPI flash, 264K SRAM). */ /* Linker script for Rad1o badge - (LPC4330, 1M SPI flash, 264K SRAM). */
MEMORY MEMORY
{ {

66
firmware/common/hackrf_core.c
View File

@ -470,8 +470,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
return bandwidth_hz_real != 0; return bandwidth_hz_real != 0;
} }
/* clock startup for Jellybean with Lemondrop attached /* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
Configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void) void cpu_clock_init(void)
{ {
@ -491,68 +490,34 @@ void cpu_clock_init(void)
si5351c_configure_pll_sources(&clock_gen); si5351c_configure_pll_sources(&clock_gen);
si5351c_configure_pll_multisynth(&clock_gen); si5351c_configure_pll_multisynth(&clock_gen);
#if (defined JAWBREAKER || defined HACKRF_ONE)
/* /*
* Jawbreaker clocks: * Clocks:
* CLK0 -> MAX5864/CPLD * CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD * CLK1 -> CPLD
* CLK2 -> SGPIO * CLK2 -> SGPIO
* CLK3 -> external clock output * CLK3 -> External Clock Output (power down at boot)
* CLK4 -> RFFC5072 * CLK4 -> RFFC5072 (MAX2837 on rad1o)
* CLK5 -> MAX2837 * CLK5 -> MAX2837 (MAX2871 on rad1o)
* CLK6 -> none * CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) * CLK7 -> LPC43xx (uses a 12MHz crystal by default)
*/ */
/* MS3/CLK3 is the source for the external clock output. */ /* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
/* MS4/CLK4 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
#endif
#ifdef RAD1O
/* rad1o clocks:
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> SGPIO
* CLK3 -> External Clock Output
* CLK4 -> MAX2837
* CLK5 -> MAX2871
* CLK6 -> none
* CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) */
/* MS3/CLK3 is the source for the external clock output. */
si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
/* MS4/CLK4 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
/* MS5/CLK5 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */ /* MS6/CLK6 is unused. */
/* MS7/CLK7 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */ /* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
#endif
/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
sample_rate_set(10000000); sample_rate_set(10000000);
si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL); si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
// soft reset // soft reset
uint8_t resetdata[] = { 177, 0xac }; // uint8_t resetdata[] = { 177, 0xac };
si5351c_write(&clock_gen, resetdata, sizeof(resetdata)); // si5351c_write(&clock_gen, resetdata, sizeof(resetdata));
si5351c_reset_pll(&clock_gen);
si5351c_enable_clock_outputs(&clock_gen); si5351c_enable_clock_outputs(&clock_gen);
//FIXME disable I2C //FIXME disable I2C
@ -560,9 +525,8 @@ void cpu_clock_init(void)
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock); i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
/* /*
* 12MHz clock is entering LPC XTAL1/OSC input now. On * 12MHz clock is entering LPC XTAL1/OSC input now.
* Jellybean/Lemondrop, this is a signal from the clock generator. On * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
* Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input. * Set up PLL1 to run from XTAL1 input.
*/ */

2
firmware/common/rffc5071.c
View File

@ -208,7 +208,7 @@ void rffc5071_enable(rffc5071_driver_t* const drv) {
} }
#define LO_MAX 5400 #define LO_MAX 5400
#define REF_FREQ 50 #define REF_FREQ 40
#define FREQ_ONE_MHZ (1000*1000) #define FREQ_ONE_MHZ (1000*1000)
/* configure frequency synthesizer in integer mode (lo in MHz) */ /* configure frequency synthesizer in integer mode (lo in MHz) */

57
firmware/common/si5351c.c
View File

@ -116,11 +116,11 @@ void si5351c_configure_pll_sources(si5351c_driver_t* const drv)
/* MultiSynth NA (PLLA) and NB (PLLB) */ /* MultiSynth NA (PLLA) and NB (PLLB) */
void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv) void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv)
{ {
//init plla to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode /*PLLA: 25MHz XTAL * (0x0e00+512)/128 = 800mhz -> int mode */
uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 }; uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
/* 10 MHz input on CLKIN for PLLB */ /*PLLB: 10MHz CLKIN * (0x2600+512)/128 = 800mhz */
data[0] = 34; data[0] = 34;
data[4] = 0x26; data[4] = 0x26;
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
@ -164,11 +164,16 @@ void si5351c_configure_multisynth(si5351c_driver_t* const drv,
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
} }
#if (defined JAWBREAKER || defined HACKRF_ONE)
void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source) void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source)
{ {
uint8_t pll; uint8_t pll;
#ifdef RAD1O
(void) source;
/* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A;
#endif
#if (defined JAWBREAKER || defined HACKRF_ONE)
if (source == PLL_SOURCE_CLKIN) { if (source == PLL_SOURCE_CLKIN) {
/* PLLB on CLKIN */ /* PLLB on CLKIN */
pll = SI5351C_CLK_PLL_SRC_B; pll = SI5351C_CLK_PLL_SRC_B;
@ -176,29 +181,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
/* PLLA on XTAL */ /* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A; pll = SI5351C_CLK_PLL_SRC_A;
} }
uint8_t data[] = {16
,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
};
si5351c_write(drv, data, sizeof(data));
}
#endif #endif
#ifdef RAD1O
void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source)
{
(void) source;
uint8_t pll;
/* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A;
/* Clock to CPU is deactivated as it is not used and creates noise */ /* Clock to CPU is deactivated as it is not used and creates noise */
/* External clock output is deactivated as it is not used and creates noise */ /* External clock output is deactivated as it is not used and creates noise */
uint8_t data[] = {16 uint8_t data[] = {16
@ -206,31 +189,24 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV
,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
}; };
si5351c_write(drv, data, sizeof(data)); si5351c_write(drv, data, sizeof(data));
} }
#endif
void si5351c_enable_clock_outputs(si5351c_driver_t* const drv) void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
{ {
#ifdef RAD1O
/* Enable CLK outputs 0, 1, 2, 4, 5 only. */ /* Enable CLK outputs 0, 1, 2, 4, 5 only. */
/* 7: Clock to CPU is deactivated as it is not used and creates noise */ /* 7: Clock to CPU is deactivated as it is not used and creates noise */
/* 3: External clock output is deactivated as it is not used and creates noise */ /* 3: External clock output is deactivated by default */
uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))}; uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
#else si5351c_write(drv, data, sizeof(data));
/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ }
uint8_t data[] = { 3, 0x40 };
#endif
si5351c_write(drv, data, sizeof(data));
}
void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){
void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){
uint8_t data[] = {16, 0}; uint8_t data[] = {16, 0};
if(ms_number < 8){ if(ms_number < 8){
@ -244,8 +220,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
si5351c_write(drv, data, 2); si5351c_write(drv, data, 2);
} }
}
}
void si5351c_set_clock_source(si5351c_driver_t* const drv, const enum pll_sources source) void si5351c_set_clock_source(si5351c_driver_t* const drv, const enum pll_sources source)
{ {

20
firmware/cpld/sgpio_if/README.md
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@ -8,20 +8,6 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:
* Xilinx WebPACK 13.4 for Windows or Linux. * Xilinx WebPACK 13.4 for Windows or Linux.
To program the SVF file into the CPLD:
* Dangerous Prototypes Bus Blaster v2:
* Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic).
* Connected to CPLD JTAG signals on Jellybean.
* urJTAG built with libftdi support.
* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
in the "Device Models" Support Resources section of the CoolRunner-II
Product Support & Documentation page. Only one file from the BSDL package is
required, and the "program" script below expects it to be at the relative
path "bsdl/xc2c/xc2c64.bsd".
Generate an XSVF Generate an XSVF
================ ================
@ -44,8 +30,4 @@ After generating a programming file:
To Program To Program
========== ==========
./program $ hackrf_cpldjtag -x default.xsvf
...which connects to the Bus Blaster interface 0, sets the BSDL directory,
detects devices on the JTAG chain, and writes the sgpio_if.svf file to the
CPLD.

10
firmware/cpld/sgpio_if/program
View File

@ -1,10 +0,0 @@
#!/bin/sh
echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2
jtag <<COMMANDSEND
cable jtagkey vid=0x0403 pid=0x6010 interface=0 driver=ftdi-mpsse
bsdl path bsdl/xc2c
detect
svf default.svf progress stop
COMMANDSEND

37
firmware/cpld/sgpio_if_passthrough/README.md
View File

@ -1,37 +0,0 @@
CPLD interface to expose LPC43xx microcontroller SGPIO peripheral, either
as all inputs or all outputs.
Requirements
============
To build this VHDL project and produce an SVF file for flashing the CPLD:
* Xilinx WebPACK 13.4 for Windows or Linux.
* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
in the "Device Models" Support Resources section of the CoolRunner-II
Product Support & Documentation page. Only one file from the BSDL package is
required, and the "program" script below expects it to be at the relative
path "bsdl/xc2c/xc2c64.bsd".
To program the SVF file into the CPLD:
* Dangerous Prototypes Bus Blaster v2:
* Configured with JTAGKey buffers.
* Connected to CPLD JTAG signals on Jellybean.
* urJTAG built with libftdi support.
To Program
==========
./program
...which connects to the Bus Blaster interface 0, sets the BSDL directory,
detects devices on the JTAG chain, and writes the sgpio_if_passthrough.svf
file to the CPLD.
Usage:
B1AUX9=0 control SGPIO0 to 15 as Input. B2AUX[1-16] => SGPIO[0-15]
B1AUX9=1 control SGPIO0 to 15 as Output. SGPIO[0-15] => B2AUX[1-16]

10
firmware/cpld/sgpio_if_passthrough/program
View File

@ -1,10 +0,0 @@
#!/bin/sh
echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2
jtag <<COMMANDSEND
cable jtagkey vid=0x0403 pid=0x6010 interface=0 driver=ftdi-mpsse
bsdl path bsdl/xc2c
detect
svf sgpio_if_passthrough.svf progress stop
COMMANDSEND

2079
firmware/cpld/sgpio_if_passthrough/sgpio_if_passthrough.svf
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File diff suppressed because it is too large Load Diff

242
firmware/cpld/sgpio_if_passthrough/sgpio_if_passthrough.xise
View File

@ -1,242 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc2c64a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="VQ100" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sgpio_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-29T12:49:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8998E598855F452AB5BAE34A005D4FD5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

89
firmware/cpld/sgpio_if_passthrough/top.ucf
View File

@ -1,89 +0,0 @@
#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18;
NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18;
#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18;
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns;
NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18;
NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18;
NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18;
NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18;
NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33;
NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33;
NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33;

60
firmware/cpld/sgpio_if_passthrough/top.vhd
View File

@ -1,60 +0,0 @@
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
SGPIO : inout std_logic_vector(15 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : in std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
type transfer_direction is (to_sgpio, from_sgpio);
signal transfer_direction_i : transfer_direction;
begin
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
else from_sgpio;
DD <= (DD'high => '1', others => '0');
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
else (others => 'Z');
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
else (others => 'Z');
end Behavioral;

73
host/hackrf-tools/src/hackrf_debug.c
View File

@ -148,19 +148,82 @@ int si5351c_write_register(
return result; return result;
} }
#define SI5351C_CLK_POWERDOWN (1<<7)
#define SI5351C_CLK_INT_MODE (1<<6)
#define SI5351C_CLK_PLL_SRC (1<<5)
#define SI5351C_CLK_INV (1<<4)
#define SI5351C_CLK_SRC_XTAL 0
#define SI5351C_CLK_SRC_CLKIN 1
#define SI5351C_CLK_SRC_MULTISYNTH_0_4 2
#define SI5351C_CLK_SRC_MULTISYNTH_SELF 3
void print_clk_control(uint8_t clk_ctrl) {
uint8_t clk_src, clk_pwr;
printf("\tclock control = \n");
if(clk_ctrl & SI5351C_CLK_POWERDOWN)
printf("\t\tPower Down\n");
else
printf("\t\tPower Up\n");
if(clk_ctrl & SI5351C_CLK_INT_MODE)
printf("\t\tInt Mode\n");
else
printf("\t\tFrac Mode\n");
if(clk_ctrl & SI5351C_CLK_PLL_SRC)
printf("\t\tPLL src B\n");
else
printf("\t\tPLL src A\n");
if(clk_ctrl & SI5351C_CLK_INV)
printf("\t\tInverted\n");
clk_src = (clk_ctrl >> 2) & 0x3;
switch (clk_src) {
case 0:
printf("\t\tXTAL\n");
break;
case 1:
printf("\t\tCLKIN\n");
break;
case 2:
printf("\t\tMULTISYNTH 0 4\n");
break;
case 3:
printf("\t\tMULTISYNTH SELF\n");
break;
}
clk_pwr = clk_ctrl & 0x3;
switch (clk_pwr) {
case 0:
printf("\t\t2 mA\n");
break;
case 1:
printf("\t\t4 mA\n");
break;
case 2:
printf("\t\t6 mA\n");
break;
case 3:
printf("\t\t8 mA\n");
break;
}
}
int si5351c_read_multisynth_config(hackrf_device* device, const uint_fast8_t ms_number) { int si5351c_read_multisynth_config(hackrf_device* device, const uint_fast8_t ms_number) {
uint_fast8_t i; uint_fast8_t i, reg_base, reg_number;
uint_fast8_t reg_base; uint16_t parameters[8], clk_control;
uint16_t parameters[8];
uint32_t p1,p2,p3,r_div; uint32_t p1,p2,p3,r_div;
uint_fast8_t div_lut[] = {1,2,4,8,16,32,64,128}; uint_fast8_t div_lut[] = {1,2,4,8,16,32,64,128};
int result;
printf("MS%d:", ms_number); printf("MS%d:", ms_number);
result = hackrf_si5351c_read(device, 16+ms_number, &clk_control);
if( result != HACKRF_SUCCESS ) {
return result;
}
print_clk_control(clk_control);
if(ms_number <6){ if(ms_number <6){
reg_base = 42 + (ms_number * 8); reg_base = 42 + (ms_number * 8);
for(i=0; i<8; i++) { for(i=0; i<8; i++) {
uint_fast8_t reg_number = reg_base + i; reg_number = reg_base + i;
int result = hackrf_si5351c_read(device, reg_number, &parameters[i]); result = hackrf_si5351c_read(device, reg_number, &parameters[i]);
if( result != HACKRF_SUCCESS ) { if( result != HACKRF_SUCCESS ) {
return result; return result;
} }