diff --git a/firmware/common/LPC4330_M4_memory.ld b/firmware/common/LPC4330_M4_memory.ld index 42e217cf..b2f6b8e2 100644 --- a/firmware/common/LPC4330_M4_memory.ld +++ b/firmware/common/LPC4330_M4_memory.ld @@ -20,7 +20,7 @@ * Boston, MA 02110-1301, USA. */ -/* Linker script for HackRF Jellybean/Jawbreaker (LPC4330, 1M SPI flash, 264K SRAM). */ +/* Linker script for Rad1o badge - (LPC4330, 1M SPI flash, 264K SRAM). */ MEMORY { diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c index e64bf9c0..59bccb1e 100644 --- a/firmware/common/hackrf_core.c +++ b/firmware/common/hackrf_core.c @@ -470,8 +470,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) { return bandwidth_hz_real != 0; } -/* clock startup for Jellybean with Lemondrop attached -Configure PLL1 to max speed (204MHz). +/* clock startup for LPC4320 configure PLL1 to max speed (204MHz). Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ void cpu_clock_init(void) { @@ -491,68 +490,34 @@ void cpu_clock_init(void) si5351c_configure_pll_sources(&clock_gen); si5351c_configure_pll_multisynth(&clock_gen); -#if (defined JAWBREAKER || defined HACKRF_ONE) /* - * Jawbreaker clocks: + * Clocks: * CLK0 -> MAX5864/CPLD * CLK1 -> CPLD * CLK2 -> SGPIO - * CLK3 -> external clock output - * CLK4 -> RFFC5072 - * CLK5 -> MAX2837 + * CLK3 -> External Clock Output (power down at boot) + * CLK4 -> RFFC5072 (MAX2837 on rad1o) + * CLK5 -> MAX2837 (MAX2871 on rad1o) * CLK6 -> none - * CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) + * CLK7 -> LPC43xx (uses a 12MHz crystal by default) */ - /* MS3/CLK3 is the source for the external clock output. */ - si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */ - - /* MS4/CLK4 is the source for the RFFC5071 mixer. */ - si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */ - - /* MS5/CLK5 is the source for the MAX2837 clock input. */ - si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ - - /* MS6/CLK6 is unused. */ - /* MS7/CLK7 is the source for the LPC43xx microcontroller. */ - uint8_t ms7data[] = { 90, 255, 20, 0 }; - si5351c_write(&clock_gen, ms7data, sizeof(ms7data)); -#endif - -#ifdef RAD1O - /* rad1o clocks: - * CLK0 -> MAX5864/CPLD - * CLK1 -> CPLD - * CLK2 -> SGPIO - * CLK3 -> External Clock Output - * CLK4 -> MAX2837 - * CLK5 -> MAX2871 - * CLK6 -> none - * CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) */ - - /* MS3/CLK3 is the source for the external clock output. */ - si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */ - - /* MS4/CLK4 is the source for the MAX2837 clock input. */ + /* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */ si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ - - /* MS5/CLK5 is the source for the RFFC5071 mixer. */ + /* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */ si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */ /* MS6/CLK6 is unused. */ + /* MS7/CLK7 is unused. */ - /* MS7/CLK7 is the source for the LPC43xx microcontroller. */ - uint8_t ms7data[] = { 90, 255, 20, 0 }; - si5351c_write(&clock_gen, ms7data, sizeof(ms7data)); -#endif - - /* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */ + /* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */ sample_rate_set(10000000); si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL); // soft reset - uint8_t resetdata[] = { 177, 0xac }; - si5351c_write(&clock_gen, resetdata, sizeof(resetdata)); + // uint8_t resetdata[] = { 177, 0xac }; + // si5351c_write(&clock_gen, resetdata, sizeof(resetdata)); + si5351c_reset_pll(&clock_gen); si5351c_enable_clock_outputs(&clock_gen); //FIXME disable I2C @@ -560,9 +525,8 @@ void cpu_clock_init(void) i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock); /* - * 12MHz clock is entering LPC XTAL1/OSC input now. On - * Jellybean/Lemondrop, this is a signal from the clock generator. On - * Jawbreaker, there is a 12 MHz crystal at the LPC. + * 12MHz clock is entering LPC XTAL1/OSC input now. + * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC. * Set up PLL1 to run from XTAL1 input. */ diff --git a/firmware/common/rffc5071.c b/firmware/common/rffc5071.c index 653a28a8..d8b06ed1 100644 --- a/firmware/common/rffc5071.c +++ b/firmware/common/rffc5071.c @@ -208,7 +208,7 @@ void rffc5071_enable(rffc5071_driver_t* const drv) { } #define LO_MAX 5400 -#define REF_FREQ 50 +#define REF_FREQ 40 #define FREQ_ONE_MHZ (1000*1000) /* configure frequency synthesizer in integer mode (lo in MHz) */ diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c index 465b2370..3bdefcda 100644 --- a/firmware/common/si5351c.c +++ b/firmware/common/si5351c.c @@ -116,11 +116,11 @@ void si5351c_configure_pll_sources(si5351c_driver_t* const drv) /* MultiSynth NA (PLLA) and NB (PLLB) */ void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv) { - //init plla to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode + /*PLLA: 25MHz XTAL * (0x0e00+512)/128 = 800mhz -> int mode */ uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 }; si5351c_write(drv, data, sizeof(data)); - /* 10 MHz input on CLKIN for PLLB */ + /*PLLB: 10MHz CLKIN * (0x2600+512)/128 = 800mhz */ data[0] = 34; data[4] = 0x26; si5351c_write(drv, data, sizeof(data)); @@ -164,11 +164,16 @@ void si5351c_configure_multisynth(si5351c_driver_t* const drv, si5351c_write(drv, data, sizeof(data)); } -#if (defined JAWBREAKER || defined HACKRF_ONE) void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source) { uint8_t pll; +#ifdef RAD1O + (void) source; + /* PLLA on XTAL */ + pll = SI5351C_CLK_PLL_SRC_A; +#endif +#if (defined JAWBREAKER || defined HACKRF_ONE) if (source == PLL_SOURCE_CLKIN) { /* PLLB on CLKIN */ pll = SI5351C_CLK_PLL_SRC_B; @@ -176,29 +181,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll /* PLLA on XTAL */ pll = SI5351C_CLK_PLL_SRC_A; } - uint8_t data[] = {16 - ,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) - ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA) - }; - si5351c_write(drv, data, sizeof(data)); -} #endif - -#ifdef RAD1O -void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source) -{ - (void) source; - uint8_t pll; - - /* PLLA on XTAL */ - pll = SI5351C_CLK_PLL_SRC_A; - /* Clock to CPU is deactivated as it is not used and creates noise */ /* External clock output is deactivated as it is not used and creates noise */ uint8_t data[] = {16 @@ -206,31 +189,24 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ - ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) + ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV ,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ ,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/ }; si5351c_write(drv, data, sizeof(data)); } -#endif - void si5351c_enable_clock_outputs(si5351c_driver_t* const drv) - { -#ifdef RAD1O +void si5351c_enable_clock_outputs(si5351c_driver_t* const drv) +{ /* Enable CLK outputs 0, 1, 2, 4, 5 only. */ /* 7: Clock to CPU is deactivated as it is not used and creates noise */ - /* 3: External clock output is deactivated as it is not used and creates noise */ + /* 3: External clock output is deactivated by default */ uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))}; -#else - /* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */ - uint8_t data[] = { 3, 0x40 }; -#endif - si5351c_write(drv, data, sizeof(data)); - } + si5351c_write(drv, data, sizeof(data)); +} - - void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){ +void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){ uint8_t data[] = {16, 0}; if(ms_number < 8){ @@ -244,8 +220,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll si5351c_write(drv, data, 2); } - - } +} void si5351c_set_clock_source(si5351c_driver_t* const drv, const enum pll_sources source) { diff --git a/firmware/cpld/sgpio_if/README.md b/firmware/cpld/sgpio_if/README.md index 44fe9a8c..e56d33a6 100644 --- a/firmware/cpld/sgpio_if/README.md +++ b/firmware/cpld/sgpio_if/README.md @@ -8,20 +8,6 @@ To build this VHDL project and produce an SVF file for flashing the CPLD: * Xilinx WebPACK 13.4 for Windows or Linux. -To program the SVF file into the CPLD: - -* Dangerous Prototypes Bus Blaster v2: - * Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic). - * Connected to CPLD JTAG signals on Jellybean. - -* urJTAG built with libftdi support. - -* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com, - in the "Device Models" Support Resources section of the CoolRunner-II - Product Support & Documentation page. Only one file from the BSDL package is - required, and the "program" script below expects it to be at the relative - path "bsdl/xc2c/xc2c64.bsd". - Generate an XSVF ================ @@ -44,8 +30,4 @@ After generating a programming file: To Program ========== -./program - -...which connects to the Bus Blaster interface 0, sets the BSDL directory, -detects devices on the JTAG chain, and writes the sgpio_if.svf file to the -CPLD. +$ hackrf_cpldjtag -x default.xsvf diff --git a/firmware/cpld/sgpio_if/program b/firmware/cpld/sgpio_if/program deleted file mode 100755 index d0b097ca..00000000 --- a/firmware/cpld/sgpio_if/program +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2 - -jtag < SGPIO[0-15] -B1AUX9=1 control SGPIO0 to 15 as Output. SGPIO[0-15] => B2AUX[1-16] diff --git a/firmware/cpld/sgpio_if_passthrough/program b/firmware/cpld/sgpio_if_passthrough/program deleted file mode 100755 index 0aba6b0e..00000000 --- a/firmware/cpld/sgpio_if_passthrough/program +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -echo Program Xilinx CoolRunner-II CPLD on Jellybean, using Bus Blaster v2 - -jtag < - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/firmware/cpld/sgpio_if_passthrough/top.ucf b/firmware/cpld/sgpio_if_passthrough/top.ucf deleted file mode 100755 index cd6a2e70..00000000 --- a/firmware/cpld/sgpio_if_passthrough/top.ucf +++ /dev/null @@ -1,89 +0,0 @@ -# -# Copyright 2012 Jared Boone -# -# This file is part of HackRF. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. - -NET "CODEC_CLK" LOC="23" |FAST |IOSTANDARD=LVCMOS18; -NET "CODEC_X2_CLK" LOC="27" |FAST |IOSTANDARD=LVCMOS18; -#NET "GCLK0" LOC="22" |FAST |IOSTANDARD=LVCMOS18; - -NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK; -TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 50 ns; - -NET "DA<7>" LOC="35" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<6>" LOC="36" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<5>" LOC="37" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<4>" LOC="39" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<3>" LOC="40" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<2>" LOC="41" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<1>" LOC="42" |FAST |IOSTANDARD=LVCMOS18; -NET "DA<0>" LOC="43" |FAST |IOSTANDARD=LVCMOS18; - -NET "DD<9>" LOC="17" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<8>" LOC="18" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<7>" LOC="19" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<6>" LOC="24" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<5>" LOC="28" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<4>" LOC="29" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<3>" LOC="30" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<2>" LOC="32" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<1>" LOC="33" |FAST |IOSTANDARD=LVCMOS18; -NET "DD<0>" LOC="34" |FAST |IOSTANDARD=LVCMOS18; - -NET "B1AUX<16>" LOC="60" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<15>" LOC="58" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<14>" LOC="56" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<13>" LOC="55" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<12>" LOC="53" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<11>" LOC="52" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<10>" LOC="50" |FAST |IOSTANDARD=LVCMOS18; -NET "B1AUX<9>" LOC="49" |FAST |IOSTANDARD=LVCMOS18; - -NET "SGPIO<15>" LOC="78" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<14>" LOC="81" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<13>" LOC="90" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<12>" LOC="70" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<11>" LOC="71" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<10>" LOC="76" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<9>" LOC="91" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<8>" LOC="68" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<7>" LOC="77" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<6>" LOC="61" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<5>" LOC="64" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<4>" LOC="67" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<3>" LOC="72" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<2>" LOC="74" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<1>" LOC="79" |FAST |IOSTANDARD=LVCMOS33; -NET "SGPIO<0>" LOC="89" |FAST |IOSTANDARD=LVCMOS33; - -NET "B2AUX<16>" LOC="92" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<15>" LOC="94" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<14>" LOC="97" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<13>" LOC="99" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<12>" LOC="1" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<11>" LOC="2" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<10>" LOC="3" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<9>" LOC="4" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<8>" LOC="6" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<7>" LOC="7" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<6>" LOC="8" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<5>" LOC="9" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<4>" LOC="10" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<3>" LOC="11" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<2>" LOC="12" |FAST |IOSTANDARD=LVCMOS33; -NET "B2AUX<1>" LOC="13" |FAST |IOSTANDARD=LVCMOS33; diff --git a/firmware/cpld/sgpio_if_passthrough/top.vhd b/firmware/cpld/sgpio_if_passthrough/top.vhd deleted file mode 100755 index 55be76b6..00000000 --- a/firmware/cpld/sgpio_if_passthrough/top.vhd +++ /dev/null @@ -1,60 +0,0 @@ --- --- Copyright 2012 Jared Boone --- --- This file is part of HackRF. --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2, or (at your option) --- any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; see the file COPYING. If not, write to --- the Free Software Foundation, Inc., 51 Franklin Street, --- Boston, MA 02110-1301, USA. - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity top is - Port( - SGPIO : inout std_logic_vector(15 downto 0); - - DA : in std_logic_vector(7 downto 0); - DD : out std_logic_vector(9 downto 0); - - CODEC_CLK : in std_logic; - CODEC_X2_CLK : in std_logic; - - B1AUX : in std_logic_vector(16 downto 9); - B2AUX : inout std_logic_vector(16 downto 1) - ); - -end top; - -architecture Behavioral of top is - type transfer_direction is (to_sgpio, from_sgpio); - signal transfer_direction_i : transfer_direction; - -begin - - transfer_direction_i <= to_sgpio when B1AUX(9) = '0' - else from_sgpio; - - DD <= (DD'high => '1', others => '0'); - - B2AUX <= SGPIO when transfer_direction_i = from_sgpio - else (others => 'Z'); - - SGPIO <= B2AUX when transfer_direction_i = to_sgpio - else (others => 'Z'); - -end Behavioral; diff --git a/host/hackrf-tools/src/hackrf_debug.c b/host/hackrf-tools/src/hackrf_debug.c index 8155477c..ad6cbf78 100644 --- a/host/hackrf-tools/src/hackrf_debug.c +++ b/host/hackrf-tools/src/hackrf_debug.c @@ -148,19 +148,82 @@ int si5351c_write_register( return result; } +#define SI5351C_CLK_POWERDOWN (1<<7) +#define SI5351C_CLK_INT_MODE (1<<6) +#define SI5351C_CLK_PLL_SRC (1<<5) +#define SI5351C_CLK_INV (1<<4) +#define SI5351C_CLK_SRC_XTAL 0 +#define SI5351C_CLK_SRC_CLKIN 1 +#define SI5351C_CLK_SRC_MULTISYNTH_0_4 2 +#define SI5351C_CLK_SRC_MULTISYNTH_SELF 3 + +void print_clk_control(uint8_t clk_ctrl) { + uint8_t clk_src, clk_pwr; + printf("\tclock control = \n"); + if(clk_ctrl & SI5351C_CLK_POWERDOWN) + printf("\t\tPower Down\n"); + else + printf("\t\tPower Up\n"); + if(clk_ctrl & SI5351C_CLK_INT_MODE) + printf("\t\tInt Mode\n"); + else + printf("\t\tFrac Mode\n"); + if(clk_ctrl & SI5351C_CLK_PLL_SRC) + printf("\t\tPLL src B\n"); + else + printf("\t\tPLL src A\n"); + if(clk_ctrl & SI5351C_CLK_INV) + printf("\t\tInverted\n"); + clk_src = (clk_ctrl >> 2) & 0x3; + switch (clk_src) { + case 0: + printf("\t\tXTAL\n"); + break; + case 1: + printf("\t\tCLKIN\n"); + break; + case 2: + printf("\t\tMULTISYNTH 0 4\n"); + break; + case 3: + printf("\t\tMULTISYNTH SELF\n"); + break; + } + clk_pwr = clk_ctrl & 0x3; + switch (clk_pwr) { + case 0: + printf("\t\t2 mA\n"); + break; + case 1: + printf("\t\t4 mA\n"); + break; + case 2: + printf("\t\t6 mA\n"); + break; + case 3: + printf("\t\t8 mA\n"); + break; + } +} + int si5351c_read_multisynth_config(hackrf_device* device, const uint_fast8_t ms_number) { - uint_fast8_t i; - uint_fast8_t reg_base; - uint16_t parameters[8]; + uint_fast8_t i, reg_base, reg_number; + uint16_t parameters[8], clk_control; uint32_t p1,p2,p3,r_div; uint_fast8_t div_lut[] = {1,2,4,8,16,32,64,128}; + int result; printf("MS%d:", ms_number); + result = hackrf_si5351c_read(device, 16+ms_number, &clk_control); + if( result != HACKRF_SUCCESS ) { + return result; + } + print_clk_control(clk_control); if(ms_number <6){ reg_base = 42 + (ms_number * 8); for(i=0; i<8; i++) { - uint_fast8_t reg_number = reg_base + i; - int result = hackrf_si5351c_read(device, reg_number, ¶meters[i]); + reg_number = reg_base + i; + result = hackrf_si5351c_read(device, reg_number, ¶meters[i]); if( result != HACKRF_SUCCESS ) { return result; }